Selected Research Highlights
Theory of DSP Architectures/High Level Architecture Synthesis

First Formulation of Algorithm Transformations for DSP Computing (Proc. IEEE, Dec. 1989)

First Formulation and introduction of the folding algorithm to synthesize timemultiplexed DSP circuits from dataflow graphs for specified folding sets (IEEE JSSC, Jan. 1992)

First Formulation and introduction of the unfolding algorithm to unfold or unroll digital signal processing dataflow graphs (IEEE Trans. Computers, Feb. 1991)

First formulation of retiming and folding for multirate digital signal processing dataflow graphs (IEEE TVLSI, Dec. 1998)

Retiming for twodimensional DSP dataflow graphs (IEEE TVLSI, June 1999)

First exhaustive generation of all retiming and scheduling solutions for digital signal processing dataflow graphs (IEEE TCASII, July 1998)

Loop scheduling algorithms and the MARS DSP Synthesis Tool (IEEE TCAD, March 1995)

HEAT tool for Power estimation in DSP Systems (IEEE D&T Magazine, April 2000)

A maximum cycle mean algorithm for computing iteration period bound of DSP dataflow graphs (Springer JSPS, Dec. 1995)
Pipelining, Parallel Processing, and Arbitrary Concurrency

First pipelining of IIR digital filters using scattered lookahead transformation (IEEE TASSP, PartI, July 1989)

First combined pipelining and parallel processing of IIR digital filters (IEEE TASSP, PartII, July 1989)

First approach to pipelining quantizer loop based DSP algorithms using parallelbranch and delayeddecision techniques (IEEE TCAS, July 1991)

First pipelining of lattice IIR Digital filters (IEEE TSP, April 1994)

First formulation of relaxed lookahead transformation for pipelining the LMS Adaptive filter (IEEE TCASII, Dec. 1993)

First pipelining of the QRDRLS Adaptive filter using annihilation reordering transformation (IEEE TSP, Aug. 2000)

First pipelining and parallel processing of the TomlinsonHarashima precoder (IEEE TCASI, Sept. 2007) ( IEEE TCASII, May 2008)

Arbitrary concurrency in Huffman decoders (IEEE ICASSP 1999)

Arbitrary concurrency in Arithmetic coders (IEEE TSP, Oct. 2006)

Arbitrary concurrency in CRC checks, BCH encoders, and linear feedback shift registers (IEEE TSP, Sept. 2011)
VLSI Signal Processing Architectures

An architecture for discrete wavelet transform (IEEE TVLSI, June 1993)

First optimization of FFT architectures for real input signals (IEEE TCASI, Dec. 2009)

Generalized FFT Architectures using Folding (IEEE TVLSI, June 2012)

LowEnergy Architectures for Welch Power Spectral Density (IEEE TCASI, Jan. 2014)

First architectures for multigigabit decision feedback equalizers (IEEE TVLSI, April 2005)

Pipelined parallel decision feedback decoder (IEEE TSP, Feb. 2007)

Complexity reduction in parallel FIR filter (Springer September 1997) (IEEE TCASI, Aug. 2004)

FEXT cancellation and equallization for 10gigabit ethernet (IEEE TCASI, June 2009)
VLSI Error Control Code Decoder Architectures

Architectures for arbitrarily parallel turbo decoders (IEEE TVLSI, Dec. 2002)

Joint (3,k) lowdensity parity check code/decoder (IEEE TSP, April 2004)

First parallel Viterbi decoder with logarithmic latency with respect to parallelism (IEEE TVLSI, June 2004)

New Retiming in AddCompareSelect Loop of Viterbi Decoder (IEEE Trans. Circuits and SystemsI, March 2004)

Fast factorization in softdecision ReedSolomon decoder (IEEE TVLSI, April 2005)

LowLatency Polar Code Decoder Architectures (IEEE TSP, June 2013) (IEEE TCASI, April 2014) (IEEE TVLSI, Oct. 2015)
Binary/Finite Field Arithmetic, Cryptography, and Hardware Security

A new lowpower binary adder (IEEE TVLSI, Dec. 1999)

Systolic architectures for modular multiplication (Springer JSPS, April 2002)

Highspeed architectures for the AES algorithm (IEEE TVLSI, Sept. 2004)

Highspeed architectures for elliptic curve cryptography (Springer JSPS, July 2010)

Performance Analysis of MUX Physical Unclonable Functions (IEEE TCAD, 2014)

Functional Encryption/Obfuscation of Chips using Keys that that are harder to reverse engineer (IEEE TVLSI, May 2015) (IEEE TIFS, Jan. 2018)

True Random Number Generators (ACM JETC, April 2016)
Brain/Biomedical Signal Classification, and Machine Learning

Prediction of Seizures in Epileptic Patients (Epilepsia, Oct. 2011) (IEEE TBCAS, 2016)

Brain Connectivity based Classification in Borderline Personality Disorder (NeuroImage: Clinical, 2016)

Schizophrenia Identification from MEG (IEEE TNSRE, 2016)

Diabetic Retinopathy Screening using DREAM tool (IEEE JBHI, 2014)
Molecular Signal Processing/DNA Computing

Molecular Computing using Fractional Coding (Scientific Reports, May 2018)

Molecular Computing and Sensing Systems (IEEE Trans. Molecular, Biological, and Multiscale Communications, Sept. 2015)

First DiscreteTime Signal Processing using Molecular Reactions/DNA Strands (IEEE Design & Test, May/June 2012) and (ACS Synthtic Biology, 2013)

Computing Polynomials using DNA (ACS Synthetic Biology, Jan. 2017)

Synchronous Sequential Computation with Molecular Reactions/DNA Strands (IEEE DAC2011) and (IEEE ICCAD2013)