Prof. Chris Kim’s Protégés at 2020 ISSCC

In an impressive coincidence, five alumni who earned their doctoral degrees under the guidance of  Prof. Chris Kim presented their papers at the prestigious and competitive 2020 International Solid-State Circuits Conference (ISSCC), often dubbed the Chip Olympics.

Prof. Jie Gu, Chris’ first student presented “A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators” at the conference. He earned his doctoral degree in 2008, after which he worked with Texas Instruments and Maxlinear. In 2015, Jie joined Northwestern University as an assistant professor in the department of electrical engineering and computer science. He leads the VLSI research lab in the department and his research interests include energy efficient mixed-signal computing, machine learning accelerators, and emerging neuromorphic computing design among other things.

Prof. Bongjin Kim presented a paper on “CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems.” During his doctoral studies, he held internships at Texas Instruments, IBM, and Rambus. After earning his PhD in 2015, Bongjin worked for a couple of years with Rambus before returning to academia as a postdoctoral research fellow at Stanford University. In 2017, he joined Nanyang Technological University, Singapore as assistant professor in the School of Electrical and Electronic Engineering.

Dr. Somnath Kundu, who graduated in 2016, presented “A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS.” This is his third presentation at ISSCC, having previously presented at the conference as a student. His research interest as a doctoral student was clock generator circuit design, and he is continuing work in the area with Intel.

Dr. Kichul Chun who graduated with his PhD in 2012 presented the next generation 16GB HBM memory chip for big data and AI applications. The paper is titled, “A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme.” Kichul currently is a senior manager of Samsung’s High Bandwidth Memory design team. 

Dr. Po-Wei Chiu, earned his doctoral degree in 2019 and is currently a circuit design engineer with Apple. He presented, “32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor.” The paper was a presentation of his doctoral research, and the first ever demonstration of a pulse amplitude modulation 4 (i.e. 2 bits per clock cycle) transceiver with noise cancellation performed entirely in the time domain, as opposed to in the voltage domain.

Learn more about Prof. Chris Kim’s research