Kia Bazargan

Associate Professor

Research Area: Computer-Aided Design, FPGAs

4-159 Keller Hall

Area of Expertise:

Field-programmable gate arrays, Computer-aided design of VLSI circuits and systems


Ph.D., 2000, Northwestern University, Evanston, IL, United States
M.S., 1998, Northwestern University, Evanston, IL, United States
B.S., CS, 1996, Sharif University of Technology, Tehran, Iran


National Science Foundation CAREER award, 2003


My research interests are primarily in the field of VLSI-CAD. They include FPGA physical design, reconfigurable computing, and ASIC floorplanning/placement. I do some FPGA designs as well. In the past couple of years, I have focused on Stochastic Computing, which uses an analog-like encoding scheme: numbers are represented by streams of 1’s and 0’s. The ratio of 1’s to the length of the stream shows the value as a “probability”. Simple logic can perform complex operations on stochastic streams (e.g., an AND gate can multiply two probabilities).

Advances in the FPGA technology have made them increasingly more powerful in the past decade, and their market share is increasing every year. The main reason for their popularity is their flexibility in changing designs without having to go through more fabrication cycles. However, the performance, power, and area efficiency of FPGAs lags behind their ASIC counterparts. My objective is to bridge the gap between ASICs and FPGAs by devising better architectures, CAD algorithms, and programming paradigms.


1. M. H. Najafi; S. Jamali-Zavareh; D. J. Lilja; M. D. Riedel; K. Bazargan; R. Harjani, “Time-Encoded Values for Highly Efficient Stochastic Circuits,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.PP, no.99, pp.1-14 , Jan 2017

2. Z. Wang, R. Goh, K. Bazargan, A. Scheel and N. Saraf, “Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 2, pp. 747-759, Feb. 2017.

3. Saraf, Naman, and Kia Bazargan. “Polynomial arithmetic using sequential stochastic logic.” In Proceedings of the 26th edition on Great Lakes Symposium on VLSI, pp. 245-250. ACM, 2016.

4. Najafi, M. Hassan, David J. Lilja, Marc Riedel, and Kia Bazargan. “Polysynchronous stochastic circuits.” In Design Automation Conference (ASP-DAC), 2016 21st Asia and South Pacific, pp. 492-498. IEEE, 2016.

5. Wang, Zhiheng, Naman Saraf, Kia Bazargan, and Arnd Scheel. “Randomness meets feedback: Stochastic implementation of logistic map dynamical system.” In Proceedings of the 52nd Annual Design Automation Conference, p. 132. ACM, 2015.

6. Satish Sivaswamy and Kia Bazargan, “Statistics Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs”, ACM Transactions on Reconfigurable Technology and Systems, Vol. 1, No 1, pp. 1-35, Mar 2008.

7. Wang, Gang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, and Eli Bozorgzadeh. “Statistical Analysis and Design of HARP Routing Pattern FPGAs”. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), to appear.

8. Ababei, Cristinel, Yan Feng, Brent Goplan, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, and Sachin S. Sapatnekar. “Placement and Routing in 3-D Integrated Circuits”. IEEE Design and Test, 22.6 (Nov.-Dec. 2005): 520-531.

9. Maidee, Pongstorn, Cristinel Ababei, and Kia Bazargan. “Timing-driven Partitioning-based Placement for Island Style FPGAs”. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 24.3 (March 2005): 395-406.

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