Doctoral students Meghna Madhusudan (advisor Professor Ramesh Harjani) and Susmita Dey Manasi (advisor Professor Sachin Sapatnekar) are recipients of Cadence’s Women in Technology scholarships for 2020-2021. These scholarships are awarded as part of Cadence’s mission to foster inclusion and diversity in technology programs and careers.
Meghna’s research interest lies in electronic design automation (EDA) of analog circuits, which are found in diverse applications ranging from cell phones to biomedical devices. Current industry practice involves an individual designing these circuits, and the process can take weeks or even months, and demands high levels of expertise. The time intensive nature of circuit design often causes bottlenecks in the chip design process, and raises costs. Ongoing research in analog EDA seeks to automate circuit design to speed it up, and require minimal human intervention.
Meghna is currently engaged with ALIGN (Analog Layout Intelligently Generated from Netlists), a DARPA-funded project (under its Electronics Resurgence Initiative) led by Professor Sapatnekar with Professor Harjani as collaborator. ALIGN is working on automating a complex and sensitive part of the design process: constructing the layout of devices as they will appear on the chip. These layouts are critical to the successful functioning of a circuit. A collaborative endeavor comprising University of Minnesota, Texas A&M University, and Intel, ALIGN will build software that can understand and build specific layouts in a matter of minutes. (Eventually, ALIGN aims to automatically generate analog layouts for most analog circuits in less than 24 hours.) Contrast this to a manually undertaken design process which can take several days or even weeks. However, one of the challenges of analog EDA is building robust solutions for automating a variety of analog circuits. Meghna addresses this particular challenge. Her work involves splitting an analog circuit into common circuit structures that are typically found across a variety of different types of analog circuits, and framing the automation methodology to build these common structures in the best possible way.
IMPLICATIONS OF MEGHNA’S RESEARCH
Successful implementation will result in significant savings in time while retaining high levels of accuracy. Automation of the design of analog circuits releases the bottleneck in the chip design process, while opening up the opportunity to explore and utilize the design space more efficiently. The outcome is improved circuit performance when compared to a manual chip design process.
Another significant outcome that Meghna hopes to achieve is industry wide acceptance of analog EDA. For many years, designers in the industry have been sceptical of the tools built by EDA researchers due to issues such as predictability and control. But Meghna hopes that with her use of the building block method, an approach similar to what is used in the manual design process prevalent in the industry, she can overcome current reluctance while also providing savings in time and other resources. The ALIGN group has been working on this particular challenge by running Intel circuit designs through the tool, and by working closely with industry entities so the tool can be built keeping in mind designers’ needs.
MEGHNA’S ACADEMIC CAREER
Meghna’s undergraduate years had a formative influence on her interest in analog circuits. She undertook projects that involved designing common analog circuits for applications such as the low noise amplifier (LNA) for an RF receiver block that is commonly used in cellular communications. An undergraduate internship designing a software tool proved to be eye opening: Meghna realized that while the specific application she was working on did not excite her, she did have a passion for programming, and programming for a hardware application would be the best of both worlds. Coming to the University of Minnesota was an easy decision: Professor Harjani’s work in analog circuit design was an obvious choice for her. His research and professional experience has been a career inspiration for Meghna, and participation in ALIGN has been in many ways the ideal research opportunity. The work carried out in the project is gaining traction within the EDA community and Meghna presented the research conducted by the group at the DARPA IDEA and POSH program meetings in early 2019, and at the ERI summit in summer 2019.
Meghna views the Cadence scholarship as a significant morale booster. The award affords her the opportunity to invest further in her field of interest in the form of courses, conferences, workshops, and also share her work broadly within the EDA community.
Susmita’s research interest is in the area of domain-specific custom hardware platforms for deep learning (DL) applications, and algorithmic optimizations in VLSI design automation. As part of her research, she has developed an analytical energy simulator for convolutional neural network (CNN) workloads on ASIC-based (application-specific integrated circuit) DL accelerators. Titled CNNergy, the simulator accounts for the complexities of scheduling computations over multidimensional data, while capturing key parameters to automatically map neural computation on the backend hardware. She has also applied CNNergy to drive energy-efficient partitioning of CNN workloads on cloud-connected mobile clients. As part of her effort to expand available tools for ASIC-based DL hardware, Susmita has also developed DeepOpt, a framework which performs layer-specific and hardware-specific scheduling of deep learning workloads to optimize the energy and throughput of the hardware. As a part of the VeriGOOD-ML project, a major undertaking that seeks to build a no-human-in-the-loop Verilog generator for real-time machine-learning hardware, she is currently engaged in developing a performance analyzer that can boost support for DL training on an ASIC platform.
IMPLICATIONS OF SUSMITA’S RESEARCH
Susmita’s research has the potential for far reaching impact. Given that customized neural hardware has wide applicability, and can provide performance gain that is orders of magnitude above conventional machines with CPUs, and GPUs, it is imperative to develop accurate prediction models to perform design evaluations of such hardware. Currently, DL hardware architects have access to only a limited number of tools for performance simulation and design insights. For Susmita, this has been an appealing challenge. It has motivated her to work on the development of specialized simulation platforms and optimization frameworks for domain-specific neural processors. Her work is supported by her interest in backend hardware and algorithmic optimization.
The tools developed by Susmita, CNNergy and DeepOpt, are open-source, allowing the wider community of practitioners to adapt and customize it to specific needs. Capable of providing detailed performance characteristics associated with various components of the network and hardware, the tools can be used to evaluate various design choices for the deployment of deep learning applications. Ultimately, Susmita’s goal is to contribute to the development of industry-standard tools that can guide the design process of neural engines.
SUSMITA’S ACADEMIC CAREER
Susmita’s interest in VLSI circuits and systems started in her sophomore year in college, and by her senior year, the interest was firmly cemented as she gained hands-on experience in VLSI design. Pursuing research opportunities in VLSI system designs and closely allied areas seemed a logical next step. For Susmita, the University of Minnesota was an easy choice given faculty expertise, and strength in disciplinary and interdisciplinary research.
A recipient of the Kevin and AJ KleinOsowski fellowship (2017-2018) and the Peter and Deborah Wexler Graduate Award (University of Illinois at Chicago), Susmita views her Cadence Technology Award as motivational and supportive. It gives her recognition among her peers, and encourages her to continue research in her field of interest.