“Ring Oscillator Clocks and Margins,” a paper resulting from a collaboration between ECE faculty Prof. Sachin Sapatnekar and Prof. Jordi Cortadella’s group from the Universitat Politècnica de Catalunya (UPC), has received the best paper award at the 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2016).
Modern chip technologies are susceptible to variations that cause can chip speeds to be unpredictable. This uncertainty is typically overcome at the cost of increased chip power which could, for example, drain the battery of a cell phone. An outcome of Prof. Sapatnekar’s sabbatical endeavor at the Department of Computer Science at UPC, this paper departs from the traditional approach of using a constant-frequency phase-locked loop (PLL) to generate on-chip clocks and quantifies the benefits of using an imperfect ring oscillator (RO) clock that does not guarantee a constant frequency. It is shown that the RO-based clock performs better than the PLL because its frequency tracks changes in the circuit closely, so that clock variations are a virtue rather than a liability. By analyzing the margins required to capture circuit variability in a simple way, the paper shows the RO to be a practical alternative to the PLL, providing significant improvements in circuit power and performance.