JOURNAL ARTICLES

[1]         Tanmoy Dhar, Ramesh Harjani, Sachin Sapatnekar, “An Aging Model for Current DACs, and its Application to Analyzing Lifetime Degradation in a Wireline Equalizer”, Microelectronics Reliability, 2023

[2]         S. Ramprasath, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar, “A Generalized Methodology for Well-Tap Insertion in Analog/Mixed-Signal Layout”, ACM Transactions on Design Automation of Electronic Systems, 2023

[3]         N. Karmokar, A. K. Sharma, J. Poojary, M. Madhusudan, R. Harjani and S. S. Sapatnekar, "Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2023.3238880.

[4]         Kishore Kunal, Steven M. Burns, Wenbin Xu, Arvind Sharma, Meghna Madhusudan, Jitesh Poojary, Tonmoy Dhar, Ramesh Harjani, Sachin Sapatnekar, Jiang Hu, “GNN-Based Hierarchical Annotation of Analog Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023,  doi: 10.1109/TCAD.2023.3236269

[5]         Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Sachin Sapatnekar, Ramesh Harjani, Jiang Hu, “Performance-driven Wire Sizing for Analog Integrated Circuits”, ACM Transactions on Design Automation of Electronic Systems, Vol 28, March 2023

[6]         Sanggeun Lee, Ramesh Harjani, Taehyoun Oh, Pseudo-Reference Counter-Based FLL for 6 Gbps Reference-less CDR in 65-nm CMOS" in IEEE Transactions on Circuits and Systems II: Express Briefs, Vol 69, Issue 4, pp 2096-2100, April 2022

[7]         Taehyoun Oh. Joonho Gil and Ramesh Harjani, "Linear Characteristic Analysis of Counter-Based Frequency Detector in Type-I Digital PLL”, IEEE Transactions on Circuits and System II: Express Briefs, Vol 69, Issue 2, pp 264-268, 2021

[8]         Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K Sharma, Wenbin Xu, Steven M Burns, Ramesh Harjani, Jiang Hu, Desmond A Kirkpatrick, Parijat Mukherjee, Sachin S Sapatnekar, Soner Yaldiz, “ALIGN: A System for Automating Analog Layout”, (Invited) IEEE Design and Test, Nov 2020

[9]         Shiva Jamali-Zavereh and Ramesh Harjani, “Jitter Suppression Techniques for High-Speed Sample-and-Hold Circuits”, IEEE Transactions on Circuits and Systems I: Regular papers, vol 67, issue 1, January 2020

[10]     DC, Mahendra; Chen, Jun-Yang; Peterson, Thomas; Sahu, Protyush; Ma, Bin; Mousavi, Naser; Harjani, Ramesh; Wang, Jian-Ping, “Observation of high spin-to-charge conversion by sputtered bismuth selenide thin films at room temperature”, Nano letters, July 8th 2019

[11]     Naser Mousavi, Zhiheng Wang and Ramesh Harjani, “A 0.4-1.0GHz, 47MHops/S Frequency Hopped TXR Front-End With 20dB In-Band Blocker Rejection”, (invited paper) IEEE Journal of Solid-State Circuits, July 2019

[12]     Anindya Saha and Ramesh Harjani, “A Highly Digital 1GS/s 7-bit PWM ADC in 65nm CMOS using Time Domain Quantization”, Electronic Letters, 2018

[13]     Mustafijur Rahman and Ramesh Harjani, “A 2.4GHz, Sub-1V, 2.8dB NF, 475uW Dual-Path Noise and Nonlinearity Cancelling LNA for IoT & WBAN”, (invited paper) IEEE Journal of Solid-State Circuits, 2018

[14]     Hassan M. Najafi, Shiva Jamali-Zavereh, David Lilja, Marc Riedel, Kiarash Bazargan, Ramesh Harjani, “An Overview of Time-Based Computing with Stochastic Constructs”, IEEE Micro, Nov 2017

[15]     Hundo Shin and Ramesh Harjani, “Low-Power Wideband Analog Channelization Filter Bank using Passive Polyphase-FFT Techniques”, IEEE Journal of Solid-State Circuits, June 2017

[16]     M Hassan Najafi, Shiva Jamali-Zavereh, David J. Lilja, Marc D. Riedel, Kia Bazargan and Ramesh Harjani, “Time-Encoded Values for Highly Efficient Stochastic Circuits” IEEE Transactions on VLSI, vol. PP, no.99, pp.1-14 January 2017 (Top 25 downloaded Manuscripts 2017 TVLSI)

[17]     Sudhir Kudva, Saurabh Chaubey and Ramesh Harjani, “A 4.1W/mm^2 Hybrid Inductive/Capacitive Converter for 2-140mA DVS Load Under Inductor”, Ultra-Low Power VLSI Design for Emerging Applications, Journal of Low Power Electronics and Applications, pp 1-19, April 2016

[18]     Mustafijur Rahman and Ramesh Harjani, “A sub-1V 194μW 31dB FOM 2.3-2.5 GHz Mixer-First Receiver Frontend for WBAN with Mutual Noise Cancellation”, IEEE Transactions on Microwave Theory and Techniques, April 2016

[19]     Rakesh K. Palani and Ramesh Harjani, “A 220MS/s 9bit 2X Time-Interleaved SAR ADC with a 133fF Input Capacitance and a FOM of 37fJ/conv in 65nm CMOS”, IEEE Transactions on Circuits and Systems – II, pp 1053-1057, November 2015

[20]     Ramesh Harjani, Danijela Cabric, Dejan Markovic, Brian S. Sadler, Rakesh K. Palani, Anindya Saha, Hundo Shin, Eric Rebeiz, Sina Basir-Kazeruni and Fang-Li Yuan, “Wideband Blind Signal Classification on a Battery Budget”, (invited) IEEE Communications Magazine, pp 173-181, October 2015

[21]     Taehyoun Oh and Ramesh Harjani, “Adaptive Techniques for Joint Optimization of XTC, AGC and DFE Loop Gain in High-Speed I/O”, ETRI Journal, Vol 37, No 5, pp906-916, October 2015

[22]     Mustafijur Rahman, Mohammad Elbadry and Ramesh Harjani, “An IEEE 802.15.6 Standard Compliant 2.5nJ/bit Multiband WBAN Transmitter using Phase Multiplexing and Injection Locking”, (invited) IEEE Journal of Solid-State Circuits, May 2015

[23]     Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler and Ramesh Harjani, “Passive Switched Capacitor RF Front-ends for Spectrum Sensing in Cognitive Radios”,  International Journal of Antennas and Propagation, vol. 2014, Article ID 947373, 20 pages, 2014. doi:10.1155/2014/947373

[24]     Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler and Ramesh Harjani, “Building an On-Chip Spectrum Sensor for Cognitive Radio”, (invited) IEEE Communications Magazine, Vol 52, No 4, pp 92-100, 2014

[25]     J.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman, “a 23.5GHz PLL with an Adaptively Biased VCO in 32nm SOI-CMOS”, in IEEE Transactions on Circuits and Systems I, Vol 60, No. 8, August 2013

[26]     Sudhir Kudva and Ramesh Harjani, “Fully Integrated Capacitive DC-DC Converter with All Digital Ripple Mitigation Technique”, (invited) in IEEE Journal of Solid-State Circuits, Vol 48, No.8, August 2013

[27]     Sachin Kalia, Satwik Patnaik, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry and Ramesh Harjani, “An 8GHz Multi-Beam Spatio-Spectral Beamforming Receiver Using an All-Passive Discrete Time Analog Baseband in 65nm CMOS”, (invited) in IEEE Transactions on Circuits & Systems I, August 2013

[28]     Taehyoun Oh and Ramesh Harjani, “A 12Gb/s Multi-Channel I/O using MIMO Crosstalk Cancellation and Signal Reutilization in 65nm CMOS”, in IEEE Journal of Solid-State Circuits, Vol 48, No. 6, June 2013.

[29]     Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Oliver Plouchart, Alexander V. ByLyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott Reynolds, Xin Li, Larry Pilleggi, Ramesh Harjani, Jose Tierno and Daniel Friedman, “A Linearized VCO Based 25GHz PLL with Automatic Biasing’, (invited) in IEEE Journal of Solid-State Circuits, Vol 48, No. 5, May 2013.

[30]     Bodhisatwa Sadhu, Martin Sturm, Brian Sadler and Ramesh Harjani, "Analysis and Design of a 5GS/s Analog Charge-Domain FFT for an SDR Front-End in 65nm CMOS", (invited) in IEEE Journal of Solid-State Circuits, Vol 48, No. 5, May 2013.

[31]     Mohammad Elbadry, Bodhisatwa Sadhu, Joe Qiu and Ramesh Harjani, “Dual Channel Injection-Locked Quadrature LO Generation for a 4 GHz Instantaneous Bandwidth Receiver at 21 GHz Center Frequency”, (invited) in IEEE Transactions on Microwave Theory and Techniques, Vol 6, No. 3, March 2013.

[32]     Narasimha Lanka, Satwik Patnaik and Ramesh Harjani, “Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-μm Technology, IEEE Journal of Solid-State Circuits, September 2011

[33]     Sudhir Kudva and Ramesh Harjani, “Fully Integrated On-Chip DC-DC Converter with a 450x Output Range”, (invited) in IEEE Journal of Solid-State Circuits, August 2011

[34]     Taehyoun Oh and Ramesh Harjani, “A 6 Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os”, (invited) IEEE Journal of Solid-State Circuits, August 2011

[35]     Mahmoud Reza Ahmadi, Amir Amirkhany, and Ramesh Harjani, “A 5Gbps 0.13um CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links”, (invited) CICC special issue in IEEE Journal of Solid State Circuits, August 2010

[36]     Jie Gu, Ramesh Harjani and Chris H. Kim, “Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs”, Vol. 17, Issue 2, pp 292-301, IEEE Transactions on VLSI, February 2009

[37]     Mahmoud Reza Ahmadi, Jaekyun Moon and Ramesh Harjani, “Constrained Partial Response Receivers for High-Speed Links”, IEEE Transactions on Circuits and System II, Vol 55. Issue 10, pp 1006-1010, October 2008

[38]     Kin-Joe Sham, Shubha Bommalingaiahnapallya, Mahmoud Reza Ahmadi and Ramesh Harjani, “A 3X5Gb/s Multi-Lane Low-Power 0.18um CMOS Pseudo-Random Bit Sequence Generator”, IEEE Transactions on Circuits and Systems II: Express Briefs, May 2008

[39]     Josh Wibben and Ramesh Harjani, “A High Efficiency DC-DC Converter Using 2nH Integrated Inductors”, IEEE Journal of Solid-State Circuits (invited for Special Issue on the 2007 Symposium on VLSI Circuits), April 2008

[40]     Frank Dropps and Ramesh Harjani, “Gain Calibration Technique for Increased Resolution in FRC Data Converters”, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol 53, No. 11, November 2006

[41]     Byunghoo Jung and Ramesh Harjani, “Designing LC VCOs Using Capacitive Degeneration Techniques”, International Journal of High Speed Electronics and Systems, special issue on High-Speed Mixed-Signal Integrated Circuits, October 2005.

[42]     Yongwang Ding and Ramesh Harjani, “A CMOS High Efficiency +22dBm Linear Power Amplifier, “IEEE Journal of Solid-State Circuits, Vol. 40, N0. 9, September 2005

[43]     Mi-Kyung Oh, Byunghoo Jung, Ramesh Harjani, and Dong-Jo Park, “New Noncoherent Receiver for UWB Impulse Radio”, IEEE Communications Letters, Vol 9, No.2, pp. 151-153, February, 2005

[44]     Byunghoo Jung and Ramesh Harjani, “A 20 GHz VCO with 5 GHz Tuning Range in 0.25 um SiGe BiCMOS”, IEEE Journal of Solid-State Circuits, Vol 39, No. 17, pp. 2359-2370,  December 2004

[45]     Jonghae Kim, Jackson Harvey and Ramesh Harjani, “A DC-Coupled 900 MHz ISM Band RF Front-End Design for a Wireless Telemetry Receiver”, IEEE Journal of Solid-State Circuits, Vol. 38, No. 1, pp. 126-134, January 2003

[46]     Liang Dai and Ramesh Harjani, “Design of Low-Phase-Noise CMOS Ring Oscillators”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol 49, No. 5, pp. 328-338, May 2002.

[47]     Ramesh Harjani, “A 455Mb/s MR Preamplier Design in 0 .8 µCMOS Process”, IEEE Journal of Solid-State Circuits, Vol. 36, No. 6, pp. 862-872, June 2001

[48]     Bapiraju Vinnakota and Ramesh Harjani, “DFT for Digital Detection of Analog Parametric Faults in SC Filters”  IEEE Transactions on Computer-Aided Design, Vol. 119, No. 7, pp. 789-798, July 2000

[49]     Liang Dai and Ramesh Harjani, “CMOS Switched-Opamp based Sample-and-Hold Circuit”, IEEE Journal of Solid-State Circuits, Vol. 35, No. 1, pp, 109-113, January, 2000

[50]     Ramesh Harjani, Randy Heineke and Feng Wang, “An Integrated Low-Voltage Class AB CMOS OTA”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 2, pp. 134-142, February 1999

[51]     Feng Wang and Ramesh Harjani, “Power Analysis and  Optimal Design of Opamps for Oversampled Converters”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 46, No. 4, pp 359-369, April, 1999

[52]     Ramesh Harjani and Tom Lee, “FRC: A Method for Extending the Resolution of Nyquist Rate Converters using Oversampling”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 45, No. 4, pp 482-494, April 1998

[53]     Ramesh Harjani, Ray Barnett, Mike Butenhoff, “BiCMOS implementation of a 276 MS/s forward equalizer and 200 MS/s FDTS detector”, IEEE Transactions on Magnetics. Vol. 34, No. 1, Part 1, p 160-165, January 1998.

[54]     Bapiraju Vinnakota and Ramesh Harjani, “Analog Circuit Observer Blocks”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing,  Vol. 44, No., 3, p 154-163, March 1997

[55]     Ramesh Harjani, Bapiraju Vinnakota and Nicholas J. Stessman “System-Level Design for Test of Fully Differential Analog Circuits”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 10, pp 1526-1534, October 1996

[56]     Ramesh Harjani and Jianfeng Shao, “Feasibility and Performance Region Modeling of Analog and Digital Circuits”, Analog Integrated Circuits and Signal Processing- special issue on Macromodeling, Vol 10, No 1-2,  pp 23-43,  June/July 1996

[57]     Ronald V. Jowarski and Ramesh Harjani, “Analog Implementation of the FDTS/DF Detection Algorithm for Magnetic Recording”, IEEE Transactions on Magnetics, Vol. 32, No. 5, Part 1, pp. 3944-3946, 1996

[58]     Bapiraju Vinnakota and Ramesh Harjani, “Self-Initializing Memory Elements”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 42, No 7, pp. 461-472, July 1995

[59]     Ramesh Harjani, “A Low-Power CMOS VGA for 50Mb/s Disk Drive Read Channels”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 42, No. 6, pp. 370-376, June 1995

[60]     Rongtai Wang and Ramesh Harjani, “Partial Positive Feedback for Gain Enhancement of Low Power CMOS OTAs”, Analog Integrated Circuits and Signal Processing, Vol. 8, No 1, pp. 21-35, July 1995

[61]     Feng Wang and Ramesh Harjani, “An Improved Model for the Slewing Behavior of Opamps” IEEE Transactions on Circuits and Systems II, Vol. 42, No. 10, pp 679-681,  October 1995

[62]     Ramesh Harjani, “Designing Mixed-Signal ICs”,  IEEE Spectrum, Vol. 29, No. 11, pp. 49-51, November  1992  (Invited paper)

[63]     Ramesh Harjani, Rob A. Rutenbar and L. Richard Carley, "OASYS: A Framework for Analog Circuit Synthesis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol., No 12, pp. 1247-1266, December 1989.

CONFERENCE PAPERS

[64]     S. Ramprasath, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar, “Analog/Mixed-Signal Layout Optimization using Optimal Well Taps”, Proc. International Symposium on Physical Design, Apr 2022

[65]     Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar, “Common-Centroid Layout for Active and Passive Devices: A review and the road ahead”, (invited) ASPDAC 2022

[66]     Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani and Jiang Hu, “Are Analytical Techniques Worthwhile for Analog IC Placement?”, DATE 2022

[67]     Nibedita Karmokar, Arvind Kumar Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani and Sachin S. Sapatnekar, “Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays”, DATE 2022

[68]     Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven Burns, Ramesh Harjani and Sachin S. Sapatnekar, “A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement”, DATE 2022

[69]     Ramprasath S, Arvind Kumar Sharma, Meghna Madhusudan, Soner Yaldiz, Jitesh Poojary, Ramesh Harjani, Steven M. Burns and Sachin S. Sapatnekar, “Analog/Mixed-Signal Layout Optimization using Optimal Well Taps”, ISPD 2022

[70]     Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Sachin Sapatnekar, Ramesh Harjani and Jiang Hu, “A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing”, 3rd ACM/IEEE Workshop on Machine Learning for CAD (MLCAD), 2021

[71]     Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta and Mike Chen, “From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2021

[72]     Arvind Kumar Sharma, Meghna Madhusudan, Steven Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani and Sachin S. Sapatnekar, “Performance-Aware Common-centroid Placement and Routing of Transistor Arrays in Analog Circuits”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2021

[73]     T. Dhar J. Poojary, Y. Li, K. Kunal, M. Madhusudan, AK Sharma, S.D. Manasi, J. Hu, R. Harjani, S. S. Sapatnekar., "Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models," 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC), 2021, pp. 158-163.

[74]     T. Dhar, K. Kunal, Y. Li, Y. Lin M. Madhusudan, J. Poojary, AK Sharma, S.M. Burns, R. Harjani, J. Hu, P. Mukherjee, S. Yaldiz, S.S. Sapatnekar, “Machine Learning Techniques in Analog Layout Automation”, Proc. of Int. Symp on Physical Design, pp 71-72,  2021

[75]     Sanjoy Basak, Yashodharma Bhat Parthaje and Ramesh Harjani, “A 0.5 GHz, 50 MHops/s Frequency Hopped Wireless Frontend with Multipath Resilience”, IMS Atlanta June 10, 2021

[76]     Arvind Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar, “Common-Centroid Layouts for Analog Circuits: Advantages and Limitations”, DATE March 2021

[77]     Meghna Madhusudan, Arvind K. Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar and Ramesh Harjani, “Analog Layout Generation using Optimized Primitives”, DATE February 2021

[78]     Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani and Sachin S. Sapatnekar, “Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models”, ASP-DAC, Jan 2021

[79]     Tonmoy Dhar, J. Poojary, R. Harjani, and S. S. Sapatnekar “Aging of Current DACs and Its Impact in Equalizer Circuits”, IEEE International Reliability Physics Symposium (IRPS), March 2021

[80]     Ramesh Harjani, Sanjoy Basak and Yashodharma Bhat Parthaje, “A 0.4-1.0 GHz, 100 MHops/s Frequency Hopped Transceiver Frontend with Multipath Resilience”, GOMACTech (virtual) March 29, 2021

[81]     Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Wenbin Xu, Sachin S Sapatnekar, Ramesh Harjani, Jiang Hu., "A Customized Graph Neural Network Model for Guiding Analog IC Placement," 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-9.

[82]     Jitesh Poojary and Ramesh Harjani, “A 1-to-3GHz Co-Channel Blocker Resistant, Spatially and Spectrally Passive MIMO Receiver in 65nm CMOS with +6dBm in-Band/In-Notch B1dB”, ISSCC Feb 2021

[83]     Tonmoy Dhar, Kishor Kunal, Yagyuang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jian Hu, Parijat Mukerjee, Soner Yaldiz, Sachin S. Sapatnekar, “The ALIGN Open-Source Analog Generator: v1.0 and Beyond”, (Invited), IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020

[84]     Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani and Sachin S. Sapatnekar, “A General Approach for Identifying Hierarchical Symmetry Constraints for Analog Circuit Layout”,  IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Sept 2020

[85]     Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Wenbin Xu, Sachin Sapatnekar, Ramesh Harjani, Jiang Hu, “Exploring a Machine Learning Approach to Performance Driven Analog IC Placement”, ISVLISI, Jul 6-8, 2020, Limassol, Cypress

[86]     Kishor Kunal, Tonmoy Dhar, Yaguang LI, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee and Sachin S. Sapatnekar, “Learning from Experience: Applying ML to Analog Circuit Design”, Proc. of International Symposium on Physical Design (ISPD), September 2020

[87]     Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind Sharma, Wenbin Xu, Steven Burns, Jiang Hu, Ramesh Harjani and Sachin S. Sapatnekar, “ GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits”, In Proceedings of the Design Automation and Test in Europe Conference (DATE), March 2020, Grenoble France (nominated for Best Paper Award).

[88]     Arvind K. Sharma, Meghna Madhusudan, Kishor Kunal, Wenbin Xu, Yaguang Li, Tonmoy Dhar, Jitesh Poojary, Vidya A. Chhabria, Steven M. Burns, Parijat Mukherjee, Desmond A. Kirkpatrick, Jiang Hu, Ramesh Harjani and Sachin S. Sapatnekar, “A Grid-based Technology-Independent Analog Cell Genertor”, Workshop on Open-Source EDA Technology (WOSET) Nov 2019

[89]     Saurabh Chaubey, Meghna Madhusudan and Ramesh Harjani,, “Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators”, (invited) IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) Dallas TX, 2019

[90]     Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, and Sachin S. Sapatnekar, “ ALIGN: Open-Source Analog Layout Automation from the Ground Up”,  (invited) In Proceedings of the 56th Annual Design Automation Conference 2019 (DAC '19).

[91]     Saurabh Chaubey and Ramesh Harjani, “A Multi-Mode DC-DC Converter for Direct Battery-to-Silicon High Tension Power Delivery in 65nm CMOS”, IEEE Custom Integrated Circuits Conference, Austin, April 2019

[92]     Ramesh Harjani, Naser Mousavi, Zhiheng Wang and Danijela Cabric, “System Tradeoffs in Ultra-Fast Frequency Hopped Transceivers”, GOMACTech, Albuquerque, NM, March 25, 2019

[93]     Mustafijur Rahman and Ramesh Harjani, “A 2.4GHz IEEE 802.15.6 Compliant 1.52nJ/bit TX & 1.32nJ/bit RX Multiband Transceiver for Low Power Standards”, International Conference on Electronics Circuits and Systems (ICECS), Bordeaux, 2018

[94]     Anindya Saha, Saurabh Chaubey and Ramesh Harjani, “A 100MS/s 9-bit Companding SAR ADC with On-Chip Input Driver in 65nm CMOS for Multi-Carrier Communications”,  IEEE International Midwest Symposium on Circuits and Systems, August 2018

[95]     Saurabh Chaubey and Ramesh Harjani, “A Zero Ripple Digital LDO With 0.6V Minimum Input Voltage, 200X Load Range and 98.7% Current Efficiency”, Techcon Sept 2018

[96]     Naser Mousavi, Zhiheng Wang and Ramesh Harjani, “A 0.4-1.0GHz, 47MHops/S Frequency Hopped TXR Front-End With 20dB In-Band Blocker Rejection”, (Best paper award) IEEE European Solid-State Circuits, Sept 2018

[97]     Qingrui Meng and Ramesh Harjani, “A 4GHz Instantaneous Bandwidth Low Squint Phased Array using Sub-Harmonic ILO Based Channelization”, IEEE European Solid-State Circuits, Sept 2018

[98]     Xingyi Hua and Ramesh Harjani, “A 5uW-5mW Input Power Range, 0-3.5V Output Voltage Range RF Energy Harvester with Power-Estimator-Enhanced MPPT Controller”, IEEE Custom Integrated Circuits Conference (CICC), April 2018

[99]     Ramesh Harjani, Danijela Cabric, Naser Mousavi and Zhiheng Wang, “An Ultra-Fast Hopping Correlator-Based Transceiver with In-Band Jammer Resistance and Multi-Path Resilience”, GOMAC 2018

[100] Saurabh Chaubey and Ramesh Harjani, “A Smart-Offset Analog LDO with 0.3V Minimum Input Voltage and 99.1% Current Efficiency”, IEEE Asian Solid-State Circuits Conference, November 2017

[101] Saurabh Chaubey and Ramesh Harjani, A Smart-Offset Analog LDO with 0.3V Minimum Input Voltage and 99.1% Current Efficiency, Techcon, September 2017

[102] Mustafijur Rahman and Ramesh Harjani, A Sub-1V, 2.8dB NF, 475uW Coupled LNA for Internet of Things Employing Dual-Path Noise and Nonlinearity Cancellation, IEEE Radio Frequency Integrated Circuits Conference (RFIC), June 2017

[103] Saurabh Chaubey and Ramesh Harjani, “Fully Tunable Software Defined DC-DC Converter with 3000X Output Current & 4X Output Voltage Range”,  IEEE Custom Integrated Circuits Conference (CICC), San Diego, April 2017

[104] Shiva Jamali-Zavareh and Ramesh Harjani, “A Jitter-Resilient Sampling Technique for High-Resolution ADCs in Wideband RF Receivers”, (invited) for special session on Advanced Concepts for Future RF and mmW Transceivers, IEEE International Conference on Electronics Circuits and Systems (ICECS), Monte Carlo, Monaco, December 2016

[105] Mustafijur Rahman and Ramesh Harjani, “CMOS Energy Efficient Integrated Radios for Emerging Low Power Standards”, (invited) to IEEE International SoC Design Conference (ISOCC), Jeju, Korea , Oct 2016

[106] Qingrui Meng and Ramesh Harjani, “An Easily Extendable FFT Based Four-Channel, Four-Beam Receiver with Progressive Partial Spatial Filtering in 65nm”, European Solid-State Circuits Conference (ESSCIRC), Lausanne, Sept 2016

[107] Hundo Shin and Ramesh Harjani, “A 1GHz Signal Bandwidth 4-Channel-I/Q Polyphase FFT Filter Bank”, European Solid-State Circuits Conference (ESSCIRC), Lausanne, Sept 2016

[108] Saurabh Chaubey and Ramesh Harjani, “A Tunable, 3000X Output Range, DC-DC Converter Using Low Leakage, 15.7fF/um2 Custom Capacitors”, Techcon, September 2016

[109] Mustafijur Rahman and Ramesh Harjani, “A sub-1V 2.8nF 475uW Coupled LNA for Internet of Things Employing Passive Mutual Noise & Non-Linearity Cancellation”, Techcon, September 2016

[110] Hundo Shin, Rakesh K. Palani, Anindya Saha, Fang-Li Yuan, Dejan Markovic and Ramesh Harjani, “An Eight Channel Analog-FFT Based 450MS/s Hybrid Filter Bank ADC With Improved SNDR for Multi-Band Signals in 40nm CMOS”, IEEE Custom Integrated Circuits Conference, September 2015

[111] Xingyi Hua and Ramesh Harjani, “3.5-0.5V Input, 1.0V Output Multi-Mode Power Transformer for a Supercapacitor Power Source with a Peak Efficiency of 70.4%”, IEEE Custom Integrated Circuits Conference, September 2015

[112] Rakesh Kumar Palani and Ramesh Harjani, “A 4.6mW, 22dBm IIP3 all MOSCAP Based 34-314MHz Tunable Continuous Time Filter in 65nm”, IEEE Custom Integrated Circuits Conference, September 2015

[113] Ramesh Harjani and Rakesh Kumar Palani, “Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages”, (Invited) IEEE Custom Integrated Circuits Conference, September 2015

[114] Rakesh Kumar Palani, Aravindhan Rangarajan and Ramesh Harjani, “Chopper Stabilized Sub 1V Reference Voltage in 65nm CMOS”, Midwest Symposium on Circuits and Systems, Fort Collins, Aug 2015

[115] Mustafijur Rahman and Ramesh Harjani, “An Ultra Low Power 2.3-2.5 GHz RF Frontend for WBAN Employing Frequency Translated Mutual Noise Cancellation (FTMNC), Techcon, September 2015

[116] Fang-Li Yuan, Rakesh Kumar Palani, Sina Basir-Kazeruni, Hundo Shin,  Anindya Saha, Ramesh Harjani and Dejan Markovic, “A Throughput-Agnostic 11.9-13.6GOPS/mW Multi-Signal Classification SoC for Cognitive Radios in 40nm CMOS”, IEEE VLSI Circuits Symposium, June 2015

[117] Chanjoon Lee, Robert Sainati, Rhonda Franklin and Ramesh Harjani, “Comparative Analysis of Frequency Selective Surface Geometry Effect in Fabry-Perot Cavity Antenna”, IEEE Wireless and Microwave Technology Conference, April 2015

[118] Mustafijur Rahman and Ramesh Harjani, “A 0.7V 194uW 31dB FOM 2.3-2.5 GHz RF Frontend for WBAN with Mutual Noise Cancellation using Passive Coupling” IEEE Radio Frequency Integrated Circuits (RFIC) May 2015

[119] Bodhisatwa Sadhu, Sachin Kalia and Ramesh Harjani, “A 3-Band Switched-Inductor LC VCO and Differential Current Re-Use Doubler Achieving 0.7-11.6GHz Turning Range”, IEEE Radio Frequency Integrated Circuits (RFIC) May 2015

[120] Chanjoon Lee, Robert Sainati, Rhonda Franklin and Ramesh Harjani, “Fluidic Switching and Tuning of Fabry-Perot Antenna”, IEEE Symposium on Antennas and Propagation, July 2015

[121] William T. Cochran, Romeo del Rosario, James Wilson, Paul Amirtharaj and Ramesh Harjani, “Challenges and Opportunities for Energy Efficient Digital Electronics”, Government Microcircuit Applications & Critical Technology Conference (GOMAC Tech), St. Louis, MO, March 2015

[122] Ramesh Harjani and Saurabh Chaubey, “A Unified Framework for Capacitive Series-Parallel DC-DC Converter Design”, (invited) IEEE Custom Integrated Circuits Conference, September 2014

[123] Sudhir Kudva, Saurabh Chaubey and Ramesh Harjani, “High Power-Density, Hybrid Inductive/Capacitive Converter with Area Reuse for Multi-Domain DVS”, IEEE Custom Integrated Circuits Conference, September 2014

[124] Rakesh Kumar Palani and Ramesh Harjani, “High Linearity PVT Tolerant  100MS/S Rail-to-Rail ADC Driver with Built-in Sampler in 65nm CMOS”, IEEE Custom Integrated Circuits Conference, September 2014

[125] Mohammad Elbadry, Sachin Kalia and Ramesh Harjani, “A 52% Tuning Range QVCO with a Reduced Noise Coupling Scheme and a Minimum FOMT of 196dBc/Hz”, IEEE Custom Integrated Circuits Conference, September 2014

[126] Saurabh Chaubey and Ramesh Harjani, “A Unified Model Based Framework for Capacitive DC-DC Converter Design”, Techcon,  September 2014

[127] Mustafijur Rahman and Ramesh Harjani, “An Ultra-Low Power Multiband WBAN Transmitter using a Novel ILO Based Modulator”, Techcon,  September 2014

[128] Mustafijur Rahman, Mohammad Elbadry and Ramesh Harjani, “A 2.5nJ/bit Multiband (MBAN & ISM) Transmitter for IEEE 802.15.6 based on a Hybrid Polyphase-MUX/ILO based Modulator”,  IEEE Radio Frequency Integrated Circuits (RFIC), (nominated for Best Paper Award) June 2014

[129] Rakesh Kumar Palani, Martin Sturm and Ramesh Harjani, “A 1.56mW 500MHz 3rd-Order Filter with Current-Mode Active-RC Biquad and 33dBm IIP3 in 65nm CMOS”, IEEE Asian Solid-State Circuits Conference, Singapore, November 2013

[130] Rakesh Kumar Palani, Martin Sturm and Ramesh Harjani, “A 1.56mW 500MHz 3rd-Order Filter with Current-Mode Active-RC Biquad and 33dBm IIP3 in 65nm CMOS”, IEEE Asian Solid-State Circuits Conference (A-SSCC),  Singapore, Nov 2013

[131] Sudhir S. Kudva and Ramesh Harjani, “A Fully Integrated, High Efficiency Combined Inductive/Capacitive Converter for Wide Output Power Range”, SRC Techcon 2013

[132] Ashutosh Mehra, Martin Sturm, Dan Hedin, and Ramesh Harjani, “A 0.32nJ/bit Noncoherent UWB Impulse Radio Transceiver with Baseband Synchronization and a Fully Digital Transmitter”,  IEEE Radio Frequency Integrated Circuits (RFIC), June 2013

[133] Sudhir S. Kudva and Ramesh Harjani, “Fully Integrated Capacitive Converter With All Digital Ripple Mitigation”, IEEE Custom Integrated Circuits Conference, September 2012 (winner Intel/Analog Devices/Catalyst Foundation CICC Student Scholarship Award)

[134] Satwik Patnaik, Sachin Kalia, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry and Ramesh Harjani, “An 8GHz Multi-Beam Spatio-Spectral Beamforming Receiver Using an All-Passive Discrete Time Analog Baseband in 65nm CMOS”, IEEE Custom Integrated Circuits Conference, September 2012

[135] Jaehyup Kim, Bruce Hammer and Ramesh Harjani, “A 5-300MHz CMOS Transceiver for Multi-Nuclear NMR Spectroscopy”, IEEE Custom Integrated Circuits Conference, September 2012

[136] J.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman “A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS”, IEEE Custom Integrated Circuits Conference, September 2012

[137] Sudhir S. Kudva and Ramesh Harjani, “Fully Integrated Capacitive Converter With All Digital Ripple Mitigation”, SRC Techcon, September 2012

[138] Taehyoun Oh and Ramesh Harjani, “Adaptive Calibration Algorithms for MIMO Channel Equalization and Crosstalk Cancellation”, SRC Techcon, September 2012 (Best Paper Award at Techcon)

[139] Bodhisatwa Sadhu, Martin Sturm, Brian Sadler and Ramesh Harjani, "CRAFT: A 5GS/s 12.2pJ/conv Analog Domain FFT for a Software Defined Radio Front-End in 65nm CMOS," IEEE RFIC, June 2012

[140] Mohammad Elbadry, Bodhisatwa Sadhu, Joe Qiu and Ramesh Harjani, " Dual Channel Injection-Locked Quadrature LO Generation for a 4GHz Instantaneous Bandwidth Receiver at 21GHz Center Frequency", (nominated for Best Paper Award) RFIC, June 2012

[141] Bodhisatwa Sadhu, Mark A. Ferrissy, Jean-Olivier Ploucharty, Arun S. Natarajany, Alexander V. Rylyakovy, Alberto Valdes-Garciay, Benjamin D. Parkery, Scott Reynoldsy, Aydin Babakhaniyx, Soner Yaldizz, Larry Pileggiz, Ramesh Harjani, Jose Tiernoy and Daniel Friedman, et. al., "A 21.8-27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve -130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier ", (nominated for Best Paper Award) RFIC, June 2012

[142] Taehyoun Oh and Ramesh Harjani, “A 10 Gb/s MIMO Channel Equalization and Crosstalk Cancellation Architecture for High-Speed I/Os”, SRC Techcon, September 2011

[143] Sudhir Kudva and Ramesh Harjani, “A Zero-Area, Zero-Power Supply Resonance Reduction Technique”, SRC Techcon, September 2011

[144] Sachin Kalia, Mohammad Elbadry, Bodhisatwa Sadhu, Satwik Patnaik and Ramesh Harjani, “A Simple, Unified Phase Noise Model for Injection-Locked Oscillators, IEEE Radio Frequency Integrated Circuits (RFIC), June 2011

[145] Sudhir Kudva and Ramesh Harjani, “Fully Integrated On-Chip DC-DC Converter with a 450X Output Range, IEEE Custom Integrated Circuits Conference, September 2010 (winner AMD/CICC Student Scholarship Award)

[146] Taehyoun Oh and Ramesh Harjani, “A 5Gb/s 2x2 MIMO Crosstalk Cancellation Scheme for High-Speed I/O, IEEE Custom Integrated Circuits Conference, September 2010 (winner AMD/CICC Student Scholarship Award)

[147] Sudhir Kudva and Ramesh Harjani, Inductors Above Digital Circuits: Towards Compact On-Chip Switching Regulators, SRC Techcon, September 2010

[148] Jaehyup Kim, Bruce Hammer and Ramesh Harjani, “A Low Power CMOS Receiver for a Tissue Monitoring NMR Spectrometer”, IEEE VLSI Circuits Symposium, June 2010

[149] Satwik Patnaik and Ramesh Harjani, “A 24-GHz Phased-Array Receiver in 0.13um CMOS using a 8-GHz LO”, IEEE Radio Frequency  Integrated Circuits (RFIC), May 2010

[150] Bodhisatwa Sadhu and Ramesh Harjani, “Capacitor Bank Design for Wide Turning Range LC VCO: 850MHz - 7.1GHz (157%)”, IEEE International Symposium on Circuits and Systems, 2010

[151] Ramesh Harjani, Jaehyup Kim, Satwik Patnaik and Bruce Hammer, “Implantable CMOS Tissue Monitoring NMR Spectrometer”, IEEE Circuits and Systems for Medical and Environmental Applications Workshop, Merida, Mexico, December 2009 (Invited)

[152] Bodhisatwa Sadhu, Jaehyup Kim and Ramesh Harjani, “A CMOS 3.3-8.4 GHz Wide Tuning Range, Low Phase Noise LC VCO”, IEEE Custom Integrated Circuits Conference, Sept 2009

[153] Mahmoud Reza Ahmadi, Amir Amirkhany and Ramesh Harjani, “A 5Gpbs 0.13um CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links”, IEEE Custom Integrated Circuits Conference, Sept 2009 (winner AMD/CICC Student Scholarship Award)

[154] Narasimha Lanka, Satwik Patnaik and Ramesh Harjani, “A Sub-2.5ns Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-$um Technology”, IEEE Custom Integrated Circuits Conference, Sept 2009

[155] Liuchun Cai and Ramesh Harjani, “1–10GHz Inductorless Receiver in 0.13um CMOS”, RFIC 2009 (nominated for Best Student Paper)

[156] Liuchun Cai and Ramesh Harjani, “Evaluating Noise Coupling Issues in Mixed-Signal 3D ICs”, DATE 2009 Friday Workshop on 3D Integration

[157] Satwik Patnaik, Narasimha Lanka and Ramesh Harjani, A Dual-Mode Architecture for a Phased-Array Receiver Based on Injection Locking in 0.13um CMOS”, IEEE International Solid-State Circuits Conference, February 2009

[158] Bodhisatwa Sadhu, Umaikhe E. Omole, and Ramesh Harjani, “Modeling and Synthesis of Wide-Band Switched-Resonators for VCOs”, IEEE Custom Integrated Circuits Conference, Sept 2008

[159] Liuchun Cai and Ramesh Harjani, “Modeling, Measurement and Mitigation of Crosstalk Noise Coupling in 3D-ICs”, IEEE Custom Integrated Circuits Conference, Sept 2008

[160] Kin-Joe Sham and Ramesh Harjani, “I/O Staggering for Low-Power Jitter Reduction”, European Microwave Conference, Aug 2008

[161] Narasimha Lanka, Satwik Patnaik and Ramesh Harjani, “Sub-10ns Frequency Hopping Synthesizer based on Injection-Locking”, European Microwave Conference, Aug 2008

[162] Ramesh Harjani and Narasimha Lanka, “High Speed Frequency Hopping Using Injection Locked RF Front-ends”, (Invited paper) Asilomar Conference on Signals, Systems, and Computers, November 2007

[163] Ramesh Harjani and Liuchun Cai, “Inductorless Design of CMOS RF Frontends”, (Invited paper), International Conference on ASIC (ASICON), October 2007

[164] Ramesh Harjani, Narasimha Lanka and Satwik Patnaik, “Fast Hopping Injection Locked Frequency Generation for UWB”, (Invited paper), IEEE International Conference on Ultra-Wideband, September 2007

[165] Narasimha Lanka, Satwik Patnaik and Ramesh Harjani, “Understanding the transient Behavior of Injection Locked Oscillators”, Techcon September 2007

[166] Mohamed Reza Ahmadi, Jaekyun Moon and Ramesh Harjani, “A Generalized Partial Response Receiver for High Speed Serial Links”, Techcon September 2007 (Best Paper in session award)

[167] Kin-Joe Sham, Shubha Bommalingaiahnapallya, Mahmoud Reza Ahmadi, and Ramesh Harjani, “A Low-power, Three-lane, 5Gbps per Lane, 0.18µm CMOS PRBS Generator”, Techcon September 2007

[168] Josh Wibben and Ramesh Harjani, A High Efficiency DC-DC Converter Using 2nH On-Chip Inductors, Symposium on VLSI Circuits, June 2007

[169] Shubha Bommalingaiahnapallya, Kin-Joe Sham, Mahmoud Reza Ahmadi, and Ramesh Harjani, “High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator”, IEEE International Symposium on Circuits and Systems, May 2007

[170] Kin-Joe Sham, Mahmoud Reza Ahmadi, Shubha Bommalingaiahnapallya, Gerry Talbot and Ramesh Harjani, FEXT Crosstalk Cancellation for High-Speed Serial Link Design, IEEE Custom Integrated Circuits Conference, September 2006.

[171] Jie Gu, Ramesh Harjani, Chris Kim, Distributed Active Decoupling Capacitors for On-Chip Supply Noise Cancellation in Digital VLSI Circuits, IEEE VLSI Circuits Symposium, June 2006

[172] Zain Asgar, Jia Zou, Priyesh Jain, Raghavendra Kamath and Ramesh Harjani , “A 20Gb/s Transceiver for Network-On-Chip”,  Future Interconnects and Networks on Chip Workshop, Munich, March, 2006

[173] Kin-Joe Sham, Mahmoud Reza Ahmadi, Shubha Bommalingaiahnapallya, Gerry Talbot and Ramesh Harjani, “Next-Generation 12.8Gbps/lane Source-Synchronous I/O Transceiver”, Techon, Sept 2005

[174] Frank Dropps and Ramesh Harjani, “High Performance FRC ADCs with Gain Calibration”, The IEE 5th International Conference Advanced A/D and D/A Conversion Techniques and Their Applications (ADDA 2005), Ireland,  25 – 27 July 2005

[175] Shubha Bommalingaiahnapallya, Ragavendra Bommalingaiahnapallya and Ramesh Harjani, “Extended Noise-Shaping In Cascaded N-Tone Sigma Delta Converters”,The IEE 5th International Conference Advanced A/D and D/A Conversion Techniques and Their Applications (ADDA 2005), Ireland,  25 – 27 July 2005

[176] Byunghoo Jung, Shubha Bommalingaiahnapallya and Ramesh Harjani, “Power Optimized LC VCO and Mixer Co-Design”, IEEE International Symposium on Circuits and Systems, May 2005

[177] Byunghoo Jung, Yi-Hung Tseng, Jackson Harvey and Ramesh Harjani, “Pulse Generator Design for UWB IR Communication Systems”, IEEE International Symposium on Circuits and Systems, May 2005

[178] Ramesh Harjani and Shubha Bommalingaiahnapallya, “Process Tolerant Design of N-Tone Sigma Delta Converters”, IEEE International Symposium on Circuits and Systems, May 2005 (Invited paper)

[179] Yong Zhan, Ramesh Harjani and Sachin S. Sapatnekar, “On the Selection of On-Chip Inductors for Optimal VCO Design” IEEE Custom Integrated Circuits Conference, October 2004

[180] Yongwang Ding and Ramesh Harjani, “A CMOS High Efficiency +22dBm Linear Power Amplifier”, IEEE Custom Integrated Circuits Conference, October 2004

[181] Wooyoung Choi, Bapiraju Vinnakota and Ramesh Harjani, “A Digital DFT Techinique for Verifying the Static Performance of A/D Converters”, IEEE Custom Integrated Circuits Conference, October 2004

[182] Jim Koeppe and Ramesh Harjani, “Enhanced Analytic Noise Model for RM CMOS Design”, IEEE Custom Integrated Circuits Conference, October 2004

[183] Byunghoo Jung and Ramesh Harjani, “A 20GHz VCO with 5GHz Tuning Range in 0.25um SiGe BiCMOS”, IEEE International Solid-State Circuits Conference, 2004

[184] Kavita Nair and Ramesh Harjani, “A 96dB SFDR 50Ms/s Digitally Enhanced CMOS Pipelined A/D Converter”, IEEE International Solid-State Circuits Conference, 2004

[185] Ramesh Harjani, Jackson Harvey and Robert Sainati, “Analog/RF Physical Layer Issues for UWB Systems”,  IEEE VLSI  Design, January 2004, (Invited paper)

[186] Byunghoo Jung and Ramesh Harjani, “A Wide Tuning Range VCO Using Capacitive Source Degeneration”, IEEE International Symposium on Circuits and Systems, May 2004

[187] Shubha B and Ramesh Harjani, “Lowpower Implementation of an N-Tone Sigma-Delta Converter”, IEEE International Symposium on Circuits and Systems, May 2004

[188] Jaewon Kim, Byunghoo Jung and Ramesh Harjani, “Novel CMOS Low-loss Transmission Line Structure”, IEEE Radio and Wireless Conference (RAWCON), September 2004

[189] Byunghoo Jung and Ramesh Harjani, “A Novel Noise Optimization Design Technique for Radio Frequency Low Noise Amplifiers”, IEEE International Symposium on Circuits and Systems, May 2003

[190] Jayant Parathasarathy and Ramesh Harjani, “Novel Integrateable Notch Filter Implementation for 100dB Image Rejection”,IEEE International Symposium on Circuits and Systems, May 2003

[191] Yongwang Ding and Ramesh Harjani, “A +18dBm IIP3 LNA in 0.35 µCMOS”, IEEE International Solid-State Circuits Conference, 2001

[192] Jonghae Kim and Ramesh Harjani, “A High Efficiency 20 dBm, 900 MHz Power Amplifier Module in 0.35 um CMOS” IEEE Radio and Wireless Conference (RAWCON) 2001

[193] Liang Dai and Ramesh Harjani, “A Low-Phase-Noise CMOS Ring Oscillator with Differential Control and Quadrature Outputs”, IEEE International ASIC/SOC Conference, 2001

[194] Ming-ta Hsieh, Jackson Harvey and Ramesh Harjani, “Power Optimization of CMOS LC VCOs”, IEEE International Symposium on Circuits and Systems, 2001

[195] Jonghae Kim and Ramesh Harjani, “An ISM Band CMOS Integrated Wireless Telemetry Transceiver (In a 0.18um Copper CMOS Process)”, IEEE Vehicular Technology Conference, 2001

[196] Wooyoung Choi and Ramesh Harjani, “Non-ideal Amplifier Effects on the Accuracy of Analog-to-Digital Capacitor Ratio Converter, IEEE International Symposium on Circuits and Systems, May 2001

[197] Ron Balczewski & Ramesh Harjani, “Capacitive Voltage Multipliers: A High Efficiency Method to Generate Multiple On-Chip Supply Voltages, IEEE International Symposium on Circuits and Systems, May 2001

[198] Jackson Harvey & Ramesh Harjani, “Analysis and design of an integrated quadrature mixer with improved noise, gain and image rejection”, IEEE International Symposium on Circuits & Systems, 5 / 2001

[199] Jackson Harvey and Ramesh Harjani, “An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage”, IEEE International Conference on VLSI Design, 2001

[200] Liang Dai and Ramesh Harjani, “Comparison and Analysis of Phase Noise in Ring Oscillators”, IEEE International Symposium on Circuits and Systems, 2000

[201] Youngwang Ding and Ramesh Harjani, “A Universal Analytic Charge Injection Model”, IEEE International Symposium on Circuits and Systems, 2000

[202] Doug Dean and Ramesh Harjani, “A High Speed Differential to Single-Ended Amplifier for Instrumentation Applications”, International Symposium on Circuits and Systems, 2000

[203] Oyvind Birkenes, Jonghae Kim and Ramesh Harjani, “An IF Stage Design For An ASK-based Wireless Telemetry System”, International Symposium on Circuits and Systems, 2000

[204] Liang Dai and Ramesh Harjani, “Analysis and Design of Low-Phase-Noise Ring Oscillators”, Liang Dai and Ramesh Harjani, International Symposium on Low Power Electronics and Design (ISLPED), 2000

[205] Ming-ta Hsieh, Jonghae Kim and Ramesh Harjani, “A European ISM Band Power Amplifier Module”, IEEE Radio and Wireless Conference (RAWCON), 2000

[206] Wooyoung Choi, Ramesh Harjani and Bapiraju Vinnakota, “Optimal Test-Set Generation for Parametric Fault Detection in Switched Capacitor Filters”, Ninth Asian Test Symposium (ATS 2000), December 2000

[207] Jonghae Kim, Jim Koeppe, Ming-ta Hsieh and Ramesh Harjani, “RF Front-End Design with Copper Passive Components”, Techcon 2000

[208] Yongwang Ding and Ramesh Harjani, “A Universal Charge Injection Model and its Applications”, Techcon 2000

[209] Jonghae Kim, Jim Koeppe, Ming-ta Hsieh and Ramesh Harjani, “A 900 MHz Front-End Design with Copper Passive Components”, Midwest Symposium on Circuits and Systems, 2000

[210] Kavita Nair and Ramesh Harjani, Compact, Ultra Low Power, Programmable Continuous-Time  Filter Banks for Feedback Cancellation in Hearing Aids, VLSI Design 1999

[211] Kavita Nair and Ramesh Harjani, “A Telemetry and Interface Circuit for Piezoelectric Sensors”, Proceedings of the IEEE International Symposium on Circuits and Systems, 1999

[212] Bapiraju Vinnakota and Ramesh Harjani, “Digital Detection of Parameteric Faults in Data Converters”, Proceedings of the IEEE Custom Integrated Circuits Conference, 1999

[213] Ramesh Harjani and Bapiraju Vinnakota, “ Digital Detection of Analog Parametric Faults in Switched-Capacitor Filter”, in Proceedings of the IEEE/ACM Design Automation Conference, 1999

[214] Oyvind Birkenes, Jonghae Kim and Ramesh Harjani , “An ISM Band RF Front-End for Short Range Wireless Telemetry”, IEEE International ASIC/SOC Conference, September 1999

[215] Jeremy Kuehlwein and Ramesh Harjani, A 273 MHz Low Noise CMOS MR Preamplifier for Disk Drives, IEEE International ASIC/SOC Conference, September 1999

[216] Jeremy Kuehlwein and Ramesh Harjani, A High Speed Low Noise CMOS MR Preamplifier for Disk Drives, European Solid-State Circuits Conference, September 1999

[217] J. Dubow, W, Zhang, Y. Lu, J. Bingham, F. Syammach,  D.G. Krantz, J. H. Belk, P. Bierman, R. Harjani, S. C. Mantell, D. L. Polla, P.R. Troyk, “Embedded Cure Monitor, Strain Gauge, and Mechanical State Estimator, SPIE, 1999

[218] T. T. Vu, P.C. Nguyen, L.T. Vu, C.H. Nguyen, M.D. Bui, A.C. Nguyen, J.N.C Vu*, R. Harjani, L.L. Kinney, K.K. Parhi, D.L. Polla, R. Schaumann, P.J. Schiller and M.S. Shur, “Gallium Arsenide Based Microsensor Systems”, Government  Microcircuit Applications Conference, 16-19 March 1998, (Best Paper award)

[219] Liang Dai and Ramesh Harjani, "CMOS Switched-Opamp Based Sample-and-Hold Circuit, Proceedings of the IEEE International Symposium on Circuits and Systems, 1998

[220] Bapiraju Vinnakota, Ramesh Harjani & Woo-Young Choi, “Pseudoduplication - An ACOB Technique for Single-Ended Circuits”, IEEE International Conference on VLSI Design, Jan 1997, p 398-402

[221] Feng Wang and Ramesh Harjani, “Nonlinear Settling Behaviour in Oversampled Converters”, Proceedings of the IEEE Custom Integrated Circuits Conference, 1997, p 495-498

[222] Kavita Nair and Ramesh Harjani, “A Ultra Low Power Transconductance Cell”, Proceedings of the IEEE International Symposium on Circuits and Systems, 1997, p 217-220

[223] Mike Gaboury and Ramesh Harjani, “Delta-Sigma-Delta Modulator: An Autoranging A/D Converter”, Proceedings of the IEEE International Symposium on Circuits and Systems, 1997, p 401-404

[224] Ray Barnett, Mike Butenhoff and Ramesh Harjani, “A BiCMOS Implementation of a 350Ms/s Forward Equalizer and 200Ms/s FDTS Detector”, Eight Magnetic Recording Conference, 1997

[225] T. T. Vu, P. C. Nguyen, L. T. Vu, C. H. Nguyen,  J. N. C. Vu, D. L. Polla, P. J. Schiller, S Stevonovich, H.Y. Li, Y. Q. Yang and Ramesh Harjani, “Gallium Arsenide Based Micro-Accelerometers”, 40th Midwest Symposium on Circuits and Systems, August 1997

[226] T. T. Vu, P.C. Nguyen, L.T. Vu, C.H. Nguyen, M.D. Bui, A.C. Nguyen, J.N.C Vu, Ramesh Harjani, L.L. Kinney, K.K. Parhi, D.L. Polla, R. Schaumann, P.J. Schiller and M.S. Shur, "Microsensors Fabricated in Gallium Arsenide", Technology 2007 (Federal Lab. Consortium, NASA and NASA Tech Briefs), 22-24 September 1997, Boston Massachusetts

[227] Feng Wang and Ramesh Harjani, “The Optimal Design of Opamps for Oversampled Converters”, Proceedings of the IEEE Custom Integrated Circuits Conference, pp 337-340, 1996

[228] Ramesh Harjani, “A Non-Slewing Opamp for Oversampled Converters”, Proceedings of the IEEE International Conference on Circuits and Systems, pp 481-484, 1996

[229] Feng Wang, Randy Heineke and Ramesh Harjani, “A Low Voltage Class AB CMOS Amplifiers”, Proceedings of the IEEE International Conference on Circuits and Systems, pp 392-396, 1996

[230] Raymond Barnett and Ramesh Harjani, “A 200MHz Differential Sampled Data FIR for Disk Drive Equalization”, Proceedings of the IEEE International Symposim on Circuits and Systems, pp 429-432, 1996

[231] Ronald V. Jowarski and Ramesh Harjani, “Analog Implementation of the FDTS/DF Detection Algorithm for Magnetic Recording”, International Magnetics Conference, 1996

[232] Feng Wang and Ramesh Harjani, “Dynamic Amplifier: Settling, Slewing and Power Issues”, in Proceedings of the IEEE International Conference on Circuits and Systems, pp. 319-322, 1995

[233] Bapiraju Vinnakota, Ramesh Harjani and Nicholas J. Stessman,  “System-level Design for Test of Fully Differential Analog Circuits”, in Proceedings of the IEEE/ACM Design Automation Conference, pp. 450-454, 1995

[234] Ramesh Harjani and Bapiraju Vinnakota, “Design of Analog Self-Checking Circuits”, in Proceedings of the IEEE International Conference on VLSI Design, pp. 67-70, Jan 1994

[235] Andrew Cable and Ramesh Harjani, “A 6-Bit 40MHz Current Subtracting Flash Converter”, in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 465-468, 1994

[236] Ramesh Harjani and Bapiraju Vinnakota, “Analog Circuit Observer Blocks”,  in Proceedings of the IEEE VLSI Test Symposium, pp. 258-263, April, 1994

[237] Jianfeng Shao and Ramesh Harjani, “Feasibility Region Modeling of Analog Circuits for Hierarchical Circuit Design”, in the Proceedings of Midwest Symposium on Circuits and Systems, pp. 407-410, 1994

[238] Jianfeng Shao and Ramesh Harjani, “Macromodeling of Analog Circuits for Hierarchical Circuit Design”, in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 656-663, 1994

[239] Rongtai Wang and Ramesh Harjani, “Acoustic Feedback Cancellation in Hearing Aids”, in Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, pp.  137-140, 1993

[240] Rongtai Wang and Ramesh Harjani, “The Suppression of Acoustic Oscillation in Hearing Aids Using Minimum Phase Techniques”, in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 818-821, 1993

[241] Brian A. Blow, Dennis L. Polla, Ramesh Harjani and T. Tamagawa, “A Dual Frequency Range Micromachined Silicon Accelerometer Architecture Using Capacitive and Piezoelectric Sensing Techniques”, in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1120-1124, 1993

[242] Ramesh Harjani, "OASYS: A Framework for Analog Circuit Synthesis", In Proceedings of The Second Annual IEEE ASIC Seminar and Exhibit, pp. P13.1/1-4, Sept 1989  (Invited paper)

[243] L. R. Carley, D. Garrod, R. Harjani, J. Kelly, T. Lim, E. Ochotta, R. A. Rutenbar, ACACIA: the CMU Analog Design System, in Proceeding of the IEEE Custom Integrated Circuits Conference, pp. 4.3/1-5, May 1989.

[244] Ramesh Harjani, Rob A. Rutenbar and L. Richard Carley, "Analog Circuit Synthesis for Performance in OASYS", in Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 492-495, Nov 1988. (Best Paper Award)

[245] Ramesh Harjani, Rob A. Rutenbar and L. Richard Carley, "Analog Circuit Synthesis & Exploration in OASYS", in Proceedings of the IEEE International Conference on Computer Design, pp. 44-47, Oct. 1988.

[246] Ramesh Harjani, Rob A. Rutenbar and L. Richard Carley, "A Prototype Framework for Knowledge-Based Analog Circuit Synthesis", in Proceedings of the IEEE/ACM Design Automation Conference, pp. 42-49, August 1987. (Best Paper Award)

Non-archival Publications

[247] Ramesh Harjani, Danijela Cabric, Dejan Markovic, Babak Daneshrad, Chuck Kryzak and Brian Sadler, “A/D-CLASIC: A Low Power Analog-FFT Based Cognitive Radio Sensor IC”, (invited) presentation at AFRL Cognitive RF Workshop, Sept 2012

[248] Ramesh Harjani, “Programmable, Software Definable and Cognitive Radios”, Silicon India, December 2009  (Invited)

[249] Shubha Bommalingaiahnapallya and Ramesh Harjani, “Multi-Rate Sigma-Delta Converter”, European Solid-State Circuits (ESSCIRC) Fringe Poster Session, September 2009

BOOKS

[250] Mustafijur Rahman and Ramesh Harjani, “Design of Low Power Integrated Radios for Emerging Standards”, Springer Scientific, Jul 2019

[251] Rakesh Palani and Ramesh Harjani, “Inverter Based Circuit Design Techniques for low supply voltages”, Springer Scientific, October 2016

[252] Mohammad Elbadry and Ramesh Harjani, “Quadrature Frequency Generation for Wideband Wireless Applications”, Springer Scientific, March, 2015

[253] Bodhisatwa Sadhu and Ramesh Harjani, “Cognitive Radio Receiver Front-Ends: RF/Analog Circuit Techniques”, Springer Scientific April 29, 2014

[254] Taehyoun Oh and Ramesh Harjani, “High Performance Multi-Channel High-Speed I/O Circuits”, Springer Scientific, September, 2013

[255] Ramesh Harjani (Editor), “Design of High-Speed Communication Circuits”, World Scientific Publishing Company, January 2006.

[256] Yongwang Ding and Ramesh Harjani, “High-Linearity CMOS RF Frontend Circuits” Kluwer Academic Publishers, October 2004

[257] Liang Dai and Ramesh Harjani, “Design of High Performance Voltage Controlled Oscillators for Communication Systems, Kluwer Academic Publishers, September, 2002

[258] Feng Wang and Ramesh Harjani, “Design of Modulators for Oversampled Converters”, Kluwer Academic Publishers, 1998

BOOK CHAPTERS

[259] Steven M. Burns, Hao Chen, Tonmoy Dhar, Ramesh Harjani, Jiang Hu, Nibedita Karmokar, Kishor Kunal, Yanguang Li, Yishuang Lin, Minguie Liu, Meghna Madhusudar, Parijat Mukerjee, David Z. Pan, Jitesh Poojary, S. Ramprasath, Sachin S. Sapatneker, Arvind K. Sharma, Wenbin Xu, Soner Yaldiz, Karen Zhu, “Machine Learning for Analog Layout”, in Machine Learning Applications in Electronic Design Automation, Edited by Haoxing Ren and Jiang Hu, Springer Verlag, 2022 (invited chapter)

[260] Ramesh Harjani, DC-DC Power Converter Designs, in DC-DC converters and voltage regulation, IEEE SSCS  CICC Tutorial book via Rivers Publishing, 2019

[261] Saurabh Chaubey, Sudhir S. Kudva and Ramesh Harjani, “Efficient On-Chip Power Management Using Fully Integrated DC-DC Converters”, in Power Management Integrated Circuits and Technology, Edited by Patrick Mercier and Mona Hella, CRC Press, ISBN 1482228939, Mar 29, 2018

[262] Bodhisatwa Sadhu and Ramesh Harjani, “Analog Signal Processing for Reconfigurable Receiver Front-Ends”, in Wireless Transceiver Circuits: System Perspectives and Design Aspects, CRC Press, 2015

[263] Ramesh Harjani, “Analog to Digital Converters”, in Analog and VLSI Circuits The Circuits and Filters Handbook 3rd Edition, Editor: Wai-Kai Chen, IEEE/CRC Press, 2009

[264] Ramesh Harjani, Rob A. Rutenbar, Gerard Maas, Philippe Magarshack, “Highlights of Mixed-Signal Design” in of ICCAD – 20 Years of Excellence in Computer Aided Design”, 2002

[265] Ramesh Harjani, Dennis Polla, Kavita Nair and Chris Zillmer, "Data Acquisition and Conversion", Wiley Encyclopedia of Electrical and Electronics Engineering, Wiley Interscience, 1999 (1st edition) & 2002 (2nd edition)

[266] Ramesh Harjani and Bapiraju Vinnakota,  "Introduction " and "Design for Test" in Analog and Mixed-Signal Test: An Overview,  Editor Bapiraju Vinnakota,  Prentice Hall, 1998

[267] Ramesh Harjani and Bapiraju Vinnakota, “ACOBs: A DFT technique for analog circuits”, Circuits and Systems in the Information Age Proceedings - IEEE International Symposium on Circuits and Systems, p 231-250 1997.

[268] Ramesh Harjani and Jianfeng Shao, “Feasibility and Performance Region Modeling of Analog and Digital Circuits”, In Modelling and Simulation of Mixed Analog-Digital Systems, Kluwer Academic Press, 1996

[269] Ramesh Harjani and Bapiraju Vinnakota, “Mixed-Signal Design Test”, in Microsystems Technology for Multimedia Applications, IEEE Press, May 1995

[270] Ramesh Harjani, “Analog to Digital Converters”, in The Circuits and Filters Handbook, Editor: Wai-Kai Chen, IEEE/CRC Press, 1995

[271] Rongtai Wang and Ramesh Harjani, “Partial Positive Feedback for Gain Enhancement of Low-Power CMOS OTAs”, in Low-Voltage Low-Power Analog Integrated Circuits, Kluwer Academic Press, 1995