Journal Publications

2024 and Preprints

  1. J. Gould and K.K. Parhi, "Backpropagation Computation for Training Graph Attention Networks," Springer Journal of Signal Processing Systems (JSPS), 96(1), pp. 1-14, Jan. 2024

  2. W. Tan, S.-W. Chiu, A. Wang, Y. Lao and K.K. Parhi, "PaReNTT: Low-Latency Parallel Residue Number System and NTT-Based Long Polynomial Modular Multiplication for Homomorphic Encryption," IEEE Trans. on Information Forensics and Security, 19, pp. 1646-1659, 2024 (Supplementary Information)

  3. X. Liu and K.K. Parhi, "Reservoir Computing with Dynamic Reservoir using Cascaded DNA Memristors," IEEE Trans. on Biomedical Circuits and Systems, 18(1), pp. 131-144, Feb. 2024 (Supplementary Information)

  4. K.K. Parhi, "Editorial: A New Era in Circuits and Systems," IEEE Circuits and Systems Magazine, 24(1), p. 3, First Quarter, 2024

  5. A. Mondal and K.K. Parhi, "Quantum Circuits for Stabilizer Error Correcting Codes: A Tutorial," IEEE Circuits and Systems Magazine, 24(1), pp. 33-51, First Quarter, 2024

  6. K.K. Parhi et al., "Editorial: Special Issue for the 75th Anniversary of the IEEE Circuits and Systems Society," IEEE Circuits and Systems Magazine, 24(2), pp. 3, Second Quarter, 2024

  7. S.-W. Chiu and K.K. Parhi, "Long Polynomial Modular Multiplication using Low-Complexity Number Theoretic Transform," IEEE Signal Processing Magazine, 41(1), pp. 92-102, Jan. 2024

  8. L. Ge and K.K. Parhi, "Robust Clustering using Hyperdimensional Computing," IEEE Open Journal of Circuits and Systems (OJCAS), 5, pp. 102-116, March 2024

  9. S.-W. Chiu and K.K. Parhi, "Low-Latency Preprocessing Architecture for Residue Number System via Flexible Barrett Reduction for Homomorphic Encryption," IEEE Transactions on Circuits and Systems II: Express Briefs, 71(5), pp. 2784-2788, May 2024 (Supplementary Information)

  10. S.S. Balaji and K.K. Parhi, "Seizure Onset Zone (SOZ) Identification using Effective Brain Connectivity of Epileptogenic Networks," Journal of Neural Engineering, 21(3), Article No. 036053, June 2024

  11. A. Mondal and K.K. Parhi, "Optimization of Quantum Circuits for Stabilizer Codes," IEEE Transactions on Circuits and Systems I: Regular Papers, 72(8), pp. 3647-3657, August 2024 (Supplementary Information)

  12. L. Ge, A.N. McInnes, A.S. Widge, and K.K. Parhi, "Determining the Number of Clusters in Clinical Response of TMS Treatment using Hyperdimensional Computing," Springer Journal of Signal Processing Systems (JSPS), June 2024

  13. W. Xu and K.K. Parhi, "Multi-Class Classification of Abnormal Heartbeat Detection using Hyperdimensional Computing," Springer Journal of Signal Processing Systems (JSPS), ePub August 2024

  14. K.K. Parhi, "Circuits and Systems Pioneers Elected to Academies in 2024," IEEE Circuits and Systems Magazine, 24(4), pp. 28-32, Fourth Quarter 2024

  15. K.K. Parhi, "Mary Jane Irwin Awarded 2024 IEEE Gustav Robert Kirchhoff Award," IEEE Circuits and Systems Magazine, 24(4), pp. 33-34, Fourth Quarter 2024

  16. K.K. Parhi, "Interview with Prof. Wenwu Zhu," IEEE Circuits and Systems Magazine, 24(4), pp. 35-37, Fourth Quarter 2024

  17. K.K. Parhi, "Interview with Prof. Gordana Jovanovic Dolecek," IEEE Circuits and Systems Magazine, 24(4), pp. 38-41, Fourth Quarter 2024

  18. S. Sanjeet, B. Sahoo, and K.K. Parhi, "SpikePipe: Accelerated Training of Spiking Neural Networks via Inter-Layer Pipelining and Multiprocessor Scheduling," IEEE Trans. on Circuits and Systems for Artificial Intelligence (TCASAI), ePub November 2024

2023

  1. N.K. Unnikrishnan and K.K. Parhi, "InterGrad: Energy-Efficient Training of Convolutional Neural Networks via Interleaved Gradient Scheduling," IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 70(5), pp. 1949-1962, May 2023 (Supplementary Information)

  2. S. Sanjeet, B. Sahoo and K.K. Parhi, "Low-Energy Real FFT Architectures and their Applications to Seizure Prediction from EEG," Analog Integrated Circuits and Signal Processing, 114, pp. 287-298, 2023

  3. S. Avvaru and K.K. Parhi, "Effective Brain Connectivity Extraction by Frequency-Domain Convergent Cross-Mapping (FDCCM) and its Application in Parkinson’s Disease Classification," IEEE Trans. on Biomedical Engineering, 70(8), pp. 2475-2485, August 2023 (Supplementary Information) (Feature)

  4. X. Liu and K.K. Parhi, "Tensor Decomposition for Model Reduction in Neural Networks: A Review [Feature]," IEEE Circuits and Systems Magazine, 23(2), pp. 8-28, Second Quarter 2023

  5. W. Tan, A. Wang, X. Zhang, Y. Lao and K.K. Parhi, "High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography," IEEE Trans. on Computers, 72(9), pp. 2454-2466, Sept. 2023

  6. N.K. Unnikrishnan, J. Gould and K.K. Parhi, "SCV-GNN: Sparse Compressed Vector-based Graph Neural Network Aggregation," IEEE Trans. on Computer Aided Design, 42(12), pp. 4803-4816, Dec. 2023

2022

  1. X. Liu and K.K. Parhi, "Reservoir Computing using DNA Oscillators," ACS Synthetic Biology, 11(2), pp. 780-787, Feb. 2022

  2. L. Ge and K.K. Parhi, "Applicability of Hyperdimensional Computing to Seizure Detection," IEEE Open Journal of Circuits and Systems (OJCAS), 3, pp. 59-71, 2022

  3. X. Zhang, Z. Huai, and K.K. Parhi, "Polynomial Multiplication Architecture with Integrated Modular Reduction for R-LWE Cryptosystems," Springer Journal of Signal Processing Systems (JSPS), 94, pp. 799-809, 2022

  4. X. Liu and K.K. Parhi, "DNA Memristors and their Application to Reservoir Computing," ACS Synthetic Biology, 11(6), pp. 2202-2213, 2022

  5. S.S. Balaji and K.K. Parhi, "Seizure Onset Zone Identification from iEEG: A Review," IEEE Access, 10, pp. 62535 - 62547, June 2022

2021

  1. B. Sen, and K.K. Parhi, "Graph-Theoretic Properties of Sub-Graph Entropy," IEEE Signal Processing Letters, 28, pp. 135-139, 2021 ( Supplementary Information)

  2. K.K. Parhi and N. K. Unnikrishnan, "Correction to "Brain-Inspired Computing: Models and Architectures"," IEEE Open Journal of Circuits and Systems, 2, pp. 291, Jan. 2021

  3. B. Sen and K.K. Parhi, "Predicting Biological Gender and Intelligence from fMRI via Dynamic Functional Connectivity," IEEE Transactions on Biomedical Engineering, 68(3), pp. 815-825, March 2021 ( Supplementary Information)

  4. K.K. Parhi, "Teaching Digital Signal Processing by Partial Flipping, Active Learning and Visualization: Keeping Students Engaged With Blended Teaching," IEEE Signal Processing Magazine, 38(3), pp. 20-29, May 2021 ( Supplementary Material)

  5. B. Sen, K.R. Cullen and K.K. Parhi, "Classification of Adolescent Major Depressive Disorder via Static and Dynamic Connectivity," IEEE Journal of Biomedical and Health Informatics (JBHI), 25(7), pp. 2604-2614, July 2021 ( Supplementary Information)

  6. S. Avvaru, N. Peled, N.R. Provenza, A.S. Widge and K.K. Parhi, "Region-Level Functional and Effective Task Engagement Network Analysis of Human Brain During Cognitive Task Engagement," IEEE Trans. Neural Systems and Rehabilitation Engineering (TNSRE), 29, pp. 1651-1660, 2021 ( Supplementary Information)

  7. S.-H. Chu, K.K. Parhi, M.W. Schreiner, C. Lenglet, B.A. Mueller, B. Klimes-Dougan, and K.R. Cullen, "Effect of SSRIs on Resting-State Functional Brain Networks in Adolescents with Major Depressive Disorder," Journal of Clinical Medicine, 10(19), Oct. 2021

  8. Y. Chen, J. Wang, S. Li, J. Xie, Q. Zhang, K.K. Parhi and X. Zeng, "A Reconfigurable 74-140 Mbps LDPC Decoding System for CCSDS Standard," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E104.A, Nov. 2021

  9. M. Liu, P. Zhou, T. Wu, K.K. Parhi, X. Zeng, and Y. Chen, "A Low-Power Twiddle Factor Addressing Architecture for Split-Radix FFT Processor," Microelectronics Journal, 117, Article 105276, Nov. 2021

  10. H. Cilasun, S. Resch, Z.I. Chowdhury, E. Olson, M. Zabihi, Z. Zhao, T. Peterson, K.K. Parhi, J.-P. Wang, S.S. Sapatnekar, and U. Karpuzcu, "Spiking Neural Networks in Spintronic Computational RAM," ACM Trans. Architecture and Code Optimization (TACO), 18(4), Article No. 59, pp. 1-24, Dec. 2021

2020

  1. Z. Zhang and K.K. Parhi, "M3U: Minimum Mean Minimum Uncertainty Feature Selection For Multiclass Classification," Springer Journal of Signal Processing Systems (JSPS), 92(1), pp. 9-22, Jan. 2020

  2. B. Sen, G.A. Bernstein, B.A. Mueller, K.R. Cullen and K.K. Parhi, "Sub-Graph Entropy based Network Approaches for Classifying Adolescent Obsessive-Compulsive Disorder from Resting-State Functional MRI," Neuroimage: Clinical, 20, Article 102208, 2020 (Supplementary Information)

  3. C. Cheng and K.K. Parhi, "Fast 2D Convolution Algorithms for Convolutional Neural Networks," IEEE Transactions on Circuits and Systems, Part-I: Regular Papers, 67(5), pp. 1678-1691, May 2020

  4. X. Liu and K.K. Parhi, "Molecular and DNA Artificial Neural Networks via Fractional Coding," IEEE Transactions on Biomedical Circuits and Systems, 14(3), pp. 490-503, June 2020 (Supplementary Material)

  5. L. Ge and K.K. Parhi, "Classification using Hyperdimensional Computing: A Review," IEEE Circuits and Systems Magazine, 20(2), pp. 30-47, June 2020

  6. S.V.S. Avvaru, Z. Zeng and K.K. Parhi, "Homogeneous and Heterogeneous Feed-Forward XOR Physical Unclonable Functions," IEEE Transactions on Information Forensics and Security, 15, pp. 2485-2498, 2020

  7. K.K. Parhi and N. K. Unnikrishnan, "Brain-Inspired Computing: Models and Architectures," IEEE Open Journal of Circuits and Systems, 1, pp. 185-204, Nov. 2020

  8. R. Mukherjee, V. Govindan, S. Koteshwara, A. Das, K.K. Parhi, and R.S. Chakraborty, "Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure," Springer Journal of Hardware and Systems Security (HASS), 4, pp. 343-360, Nov. 2020

  9. Q. Zhang, Y. Chen, S. Li, X. Zeng and K.K. Parhi, "A High-Performance Stochastic LDPC Decoder Architecture via Correlation Analysis," IEEE Transactions on Circuits and Systems, Part-I: Regular Papers, 67(12), pp. 5429-5442, Dec. 2020

2019

  1. K.K. Parhi and Y. Liu, "Computing Arithmetic Functions Using Stochastic Logic by Series Expansion," IEEE Transactions on Emerging Technologies in Computing (TETC), 7(1), pp. 44-59, March 2019

  2. S. Koteshwara, A. Das and K.K. Parhi, "Architecture Optimization and Performance Comparison of Nonce-Misuse Resistant Authenticated Encryption Algorithms," IEEE Transactions on VLSI Systems, 27(5), pp. 1053-1066, May 2019

  3. B. Sen, S.-H. Chu and K.K. Parhi, "Ranking Regions, Edges and Classifying Tasks in Functional Brain Graphs by Sub-Graph Entropy," Scientific Reports, Vol. 9, Article 7628, May 2019 ( Supplementary Information)

  4. K.K. Parhi and Z. Zhang, "Discriminative Ratio of Spectral Power and Relative Power Features Derived via Frequency-Domain Model Ratio (FDMR) with Application to Seizure Prediction," IEEE Transactions on Biomedical Circuits and Systems, 13(4), pp. 645-657, August 2019

  5. H. Bogunovic, F. Venhuizen, S. Klimscha, S. Apostolopoulos, A. Bab-Hadiashar, U. Bagci, M. Faisal Beg, L. Bekalo, Q. Chen, C. Ciller, K. Gopinath, A.K. Gostar, K. Jeon, Z. Ji, S.-H. Kang, D.D. Koozekanani, D. Lu, D. Morley, K.K. Parhi, H.-S. Park, A. Rashno, M. Sarunic, S. Shaikh, J. Sivaswamy, R. Tennakoon, S. Yadav, S. De Zanet, S.M. Waldstein, B.S. Gerendas, C. Klaver, C.I. Sanchez, U. Schmidt-Erfurth, "RETOUCH - The Retinal OCT Fluid Detection and Segmentation Benchmark and Challenge," IEEE Transactions on Medical Imaging, 38(8), pp. 1858-1874, August 2019

  6. Z. Zhang and K.K. Parhi, "MUSE: Minimum Uncertainty and Sample Elimination Based Binary Feature Selection," IEEE Transactions on Knowledge and Data Engineering (TKDE), 31(9), pp. 1750-1764, Sept. 2019

2018

  1. S. Koteshwara, C.H. Kim and K.K. Parhi, "Key-Based Dynamic Functional Obfuscation of Integrated Circuits using Sequentially-Triggered Mode-Based Design," IEEE Trans. Information Forensics and Security (TIFS), 13(1), pp. 79-93, Jan. 2018

  2. S. Chu, K.K. Parhi and C. Lenglet, "Function-specific and Enhanced Brain Structural Connectivity Mapping via Joint Modeling of Diffusion and Functional MRI," Scientific Reports, Vol. 8, Article 4741, March 2018 ( Supplementary Material )

  3. A. Rashno, D.D. Koozekanani, P.M. Drayna, B. Nazari, S. Sadri, H. Rabbani, and K.K. Parhi, "Fully-Automated Segmentation of Fluid/Cyst Regions in Optical Coherence Tomography Images with Diabetic Macular Edema using Neutrosophic Sets and Graph Algorithms," IEEE Trans. Biomedical Engineering, 65(5), pp. 989-1001, May 2018 (Supplementary Material)

  4. S.A. Salehi, X. Liu, M.D. Riedel, and K.K. Parhi, "Computing Mathematical Functions using DNA via Fractional Coding," Scientific Reports, Vol. 8, Article 8312, May 2018 ( Supplementary Material)

  5. Y. Liu and K.K. Parhi, "Linear-Phase Lattice FIR Digital Filter Architectures using Stochastic Logic," Springer Journal of Signal Processing Systems (JSPS), 90(5), pp. 791-803, May 2018

  6. Y. Lao and K.K. Parhi, "Canonic Composite Length Real-Valued FFT," Springer Journal of Signal Processing Systems (JSPS), 90(10), pp. 1401-1414, October 2018

  7. M. Garrido, N.K. Unnikrishnan and K.K. Parhi, "A Serial Commutator Fast Fourier Transform Architecture for Real-Valued Signals," IEEE Trans. on Circuits and Systems, Part-II: Express Briefs, 65(11), pp. 1693-1697, Nov. 2018

  8. K.K. Parhi, "Stochastic Logic Implementations of Polynomials with All Positive Coefficients by Expansion Methods," IEEE Transactions on Circuits and Systems, Part-II: Transactions Briefs, 65(11), pp. 1698-1702, Nov. 2018

  9. S. Koteshwara and K.K. Parhi, "Incremental-Precision based Feature Computation and Multi-Level Classification for Low-Energy Internet-of-Things," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 8(4), pp. 822-835, Dec. 2018

2017

  1. B. Yuan and K.K. Parhi, "LLR-based Successive-Cancellation List Decoder for Polar Codes with Multibit Decision," IEEE Transactions on Circuits and Systems, Part-II: Transactions Briefs, 64(1), pp. 21-25, Jan. 2017

  2. S.A. Salehi, K.K. Parhi and M.D. Riedel, "Chemical Reaction Networks for Computing Polynomials," ACS Synthetic Biology, 6(1), pp. 76-83, Jan. 2017

  3. Y. Lao, B. Yuan, C.H. Kim and K.K. Parhi, "Reliable PUF-based Local Authentication with Self-Correction," IEEE Trans. Computer Aided Design, 36(2), pp. 201-213, Feb. 2017

  4. B. Yuan and K.K. Parhi, "VLSI Architectures for the Restricted Boltzmann Machine," ACM Journal on Emerging Technologies in Computing Systems (JETC), 13(3), Article 35, May 2017

  5. Y. Liu and K.K. Parhi, "Computing Polynomials using Unipolar Stochastic Logic," ACM Journal on Emerging Technologies in Computing Systems (JETC), 13(3), Article 42, May 2017

  6. K.K. Parhi, "Takao Nishitani: An Outstanding Researcher, Technical Leader and Mentor," IEEE Solid-State Circuits Magazine, 9(2), Spring 2017

  7. Y. Lao and K.K. Parhi, "Canonic FFT Flow-Graphs for Real-Valued Even/Odd Symmetric Inputs," EURASIP Journal on Advances in Signal Processing, 2017:45, June 2017

  8. A. Rashno, B. Nazari, D. D. Koozekanani, P.M. Drayna, S. Sadri, H. Rabbani and K.K. Parhi, "Fully-Automated 2D and 3D Segmentation of Fluid Regions in Exudative Age-Related Macular Degeneration Subjects: Kernel Graph Cut in Neutrosophic Domain," PloS ONE, 12(10), e0186949, Oct. 2017

2016

  1. T. Xu, K.R. Cullen, B. Mueller, M.W. Schreiner, K.O. Lim, S.C. Schulz, and K.K. Parhi, "Network Analysis of Functional Brain Connectivity in Borderline Personality Disorder Using Resting-State fMRI," NeuroImage: Clinical, 11, pp. 302-315, 2016

  2. Z. Zhang and K.K. Parhi, "Low-Complexity Seizure Prediction From iEEG/sEEG using Spectral Power and Ratios of Spectral Power," IEEE Transactions on Biomedical Circuits and Systems, 10(3), pp. 693-706, June 2016

  3. Y. Liu and K.K. Parhi, "Architectures for Recursive Digital Filters Using Stochastic Computing," IEEE Transactions on Signal Processing, 64(14), pp. 3705-3718, July 15, 2016

  4. Y. Wang, B. Yuan, and K.K. Parhi, "Improved BER Performance with Rotated Head Array and 2D Detector in Two-Dimensional Magnetic Recording," IEEE Trans. Magnetics, 52(7), Article#3001706, July 2016

  5. T. Xu, M. Stephane and K.K. Parhi, "Abnormal Neural Oscillations in Schizophrenia Assessed by Spectral Power Ratio of MEG during Word Processing," IEEE Transactions on Neural Systems and Rehabilitation Engineering, 24(11), pp. 1148-1158, Nov. 2016 (Feature)

  6. S. Roychowdhury, D.D. Koozekanani, S.N. Kuchinka, and K.K. Parhi, "Optic Disc Boundary and Vessel Origin Segmentation of Fundus Images," IEEE Journal of Biomedical and Health Informatics, 20(6), pp. 1562-1574, Nov. 2016 (Supplementary Material)

  7. Y. Lao, Q. Tang, C.H. Kim and K.K. Parhi, "Beat Frequency Detector based High-Speed TRNGs: Statistical Modeling and Analysis," ACM Journal on Emerging Technologies in Computing Systems (JETC), 13(1), Article 9, Dec. 2016

2015

  1. Y. Lao and K.K. Parhi, "Obfuscating DSP Circuits via High-Level Transformations," IEEE Transactions on VLSI Systems, 23(5), pp. 819-830, May 2015

  2. S. Roychowdhury, D.D. Koozekanani and K.K. Parhi, "Blood Vessel Segmentation of Fundus Images by Major Vessel Extraction and Sub-Image Classification," IEEE Journal of Biomedical and Health Informatics, 19(3), pp. 1118-1128, May 2015

  3. S. Roychowdhury, D.D. Koozekanani and K.K. Parhi, "Iterative Vessel Segmentation of Fundus Images," IEEE Transactions on Biomedical Engineering, 62(7), pp. 1738-1749, July 2015 (Supplementary Material)

  4. M. Bandarabadi, J. Rasekhi, C.A. Teixeira, T.I. Netoff, K.K. Parhi, and A. Dourado, "Early Seizure Detection using Neuronal Potential Similarity: A Generalized Low-Complexity and Robust Measure," International Journal of Neural Systems (IJNS), 25(5), pp: 1550019:1-18, Aug. 2015

  5. S.A. Salehi, H. Jiang, M.D. Riedel, and K.K. Parhi, "Molecular Sensing and Computing Systems (Invited Paper)," IEEE Transactions on Molecular, Biological, and Multi-Scale Communications, 1(3), pp. 249-264, Sept. 2015

  6. B. Yuan and K.K. Parhi, "Low-Latency Successive-Cancellation List Decoders for Polar Codes with Multi-bit Decision," IEEE Transactions on VLSI Systems, 23(10), pp. 2268-2280, October 2015

2014

  1. K.K. Parhi and M. Ayinala, "Low-Complexity Welch Power Spectral Density Computation," IEEE Trans. Circuits and Systems-I: Regular Papers, 61(1), pp. 172-182, Jan. 2014

  2. R. Liu, T.-L. Kung and K.K. Parhi, "Impulse Noise Correction in OFDM Systems," Springer Journal of Signal Processing Systems, 74(2), pp. 245-262, Feb. 2014

  3. C. Zhang and K.K. Parhi, "Latency Analysis and Architecture Design of Simplified SC Polar Decoders," IEEE Trans. Circuits and Systems-II: Transactions Briefs, 61(2), pp. 115-119, Feb. 2014

  4. B. Yuan and K.K. Parhi, "Low-Latency Successive-Cancellation Polar Decoder Architectures using 2-bit Decoding," IEEE Trans. Circuits and Systems-I: Regular Papers, 61(4), pp. 1241-1254, Apr. 2014

  5. Y. Lao and K.K. Parhi "Statistical Analysis of MUX-based Physical Unclonable Functions," IEEE Trans. on Computer Aided Design, 33(5), pp. 649-662, May 2014

  6. S. Roychowdhury, D.D. Koozekanani and K.K. Parhi, "DREAM: Diabetic Retinopathy Analysis using Machine Learning," IEEE Journal of Biomedical and Health Informatics, 18(5), pp. 1717-1728, Sept. 2014, [Journal Cover]

  7. Y. Wang, B. Yuan, K.K. Parhi and R. Victora, "Two-Dimensional Magnetic Recording using a Rotated Head Array and LDPC Code Decoding," IEEE Transactions on Magnetics, 50(11), November 2014

  8. B. Yuan and K.K. Parhi, "Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders," IEEE Transactions on Signal Processing, 62(24), pp. 6496-6506, Dec. 15, 2014

2013

  1. T.-L. Kung and K.K. Parhi, "Semiblind Frequency-Domain Timing Synchronization and Channel Estimation for OFDM Systems," EURASIP Journal on Advances in Signal Processing , 2013(1), Jan. 2013

  2. Y. Hu, and K.K. Parhi, "Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits," Springer Journal of Signal Processing Systems , 70(3), pp. 259-274, March 2013

  3. T.-L. Kung and K.K. Parhi, "Performance Evaluation of Variable Transmission Rate OFDM Systems via Network Source Coding," EURASIP Journal on Advances in Signal Processing, Vol. 2013(12), 2013

  4. K.K. Parhi, "Comments on "Low-Energy CSMT Carry Generators and Binary Adders"" IEEE Trans. VLSI Systems, 21(4), p. 791, April 2013

  5. T. Xu, M. Stephane, and K.K. Parhi, "Multidimensional Analysis of Abnormal Neural Oscillations Associated with Lexical Processing in Schizophrenia," Clinical EEG & Neuroscience, 44(2), pp. 135-143, April 2013

  6. C. Zhang and K.K. Parhi, "Low-Latency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder," IEEE Trans. Signal Processing, 61(10), pp. 2429-2441, May 15, 2013

  7. H. Jiang, S.A. Salehi, M.D. Riedel, and K.K. Parhi, "Discrete-Time Signal Processing with DNA" American Chemical Society (ACS) Synthetic Biology, 2(5), pp. 245-254, 2013

  8. S.A. Salehi, R.Amirfattahi, and K.K. Parhi, "Pipelined Architectures for Real-Valued FFT and Hermitian-Symmetric IFFT with Real Datapaths," IEEE Trans. Circuits and Systems-II: Transactions Briefs, 60(8), pp. 507-511, Aug. 2013

  9. M. Ayinala and K.K. Parhi, "FFT Architectures for Real-valued Signals based on Radix-2^3 and Radix-2^4 algorithms," IEEE Trans. Circuits and Systems-I: Regular Papers, 60(9), pp. 2422-2430, Sept. 2013

  10. K.K. Parhi, "Hierarchical Folding and Synthesis of Iterative Data-Flow Graphs," IEEE Trans. Circuits and Systems-II: Transactions Briefs, 60(9), pp. 597-601, Sept. 2013

  11. T. Kung and K.K. Parhi, "Optimized Joint Timing Synchronization and Channel Estimation for Communications Systems with Multiple Transmit Antennas," EURASIP Journal on Advances in Signal Processing, 2013(139), 2013

  12. M. Ayinala, Y. Lao, and K.K. Parhi, "An In-Place FFT Architecture for Real-Valued Signals," IEEE Trans. Circuits and Systems-II: Transactions Briefs, 60(10), pp. 652-656, Oct. 2013

2012

  1. A.E. Cohen, J.-H. Lin, and K.K. Parhi, "Variable Data Rate (VDR) Network Congestion Control (NCC) Applied to Voice/Audio Communication," Computer Networks , Elsevier, 56(4), pp. 1343-1356, March 2012

  2. H. Jiang, M.D. Riedel, and K.K. Parhi, "Digital Signal processing with Molecular Reactions," IEEE Design & Test Magazine , (Special Issue on Bio-Design Automation in Synthetic Biology), 29(3), pp. 21-31, May/June 2012

  3. M. Ayinala, M.J. Brown and K.K. Parhi, "Pipelined Parallel FFT Architectures via Folding Transformation", IEEE Trans. VLSI Systems , pp. 1068-1081, 20(6), June 2012

  4. C. Zhang, and K.K. Parhi, "A Network-Efficient Non-Binary QC-LDPC Decoder Architecture", IEEE Trans. Circuits and Systems-I: Regular Papers , 59(6), pp. 1359-1371, June 2012

  5. T. Kung, and K.K. Parhi, "Optimized Joint Timing Synchronization and Channel Estimation for OFDM Systems," IEEE Wireless Communications Letters , 1(3), pp. 149-152, June 2012

  6. H.A. Patil, M.C. Madhavi, and K.K. Parhi, "Static and Dynamic Information Derived from Source and System Features for Person Recognition from Humming," Springer International Journal of Speech Technology, , 15(3), pp. 393-406, September 2012

2011

  1. A.E. Cohen and K.K. Parhi, "Secure Variable Data Rate Transmission," IEEE Trans. Circuits and Systems-II: Transactions Briefs , 58(2), pp. 100-104, Feb. 2011

  2. M. Ayinala and K.K. Parhi, "High-Speed Parallel Architectures for Linear Feedback Shift Registers", IEEE Trans. Signal Processing , 59(9), pp. 4459-4469, Sept. 2011

  3. Y. Park, L. Luo, K.K. Parhi and T. Netoff, "Seizure Prediction with Spectral Power of EEG Using Cost-Sensitive Support Vector Machines," Epilepsia , 52(10), pp. 1761-1770, Oct. 2011, (Supplementary Material) [Journal Cover]

  4. R. Liu and K.K. Parhi, "Power Reduction in Frequency-Selective FIR Filters under Voltage Overscaling," IEEE Journal on Emerging Technologies in Circuits and Systems, 1(3), pp. 343-356, Sept. 2011

  5. A.E. Cohen and K.K. Parhi, "Architecture Optimizations for the RSA Public Key Cryptosystem: A Tutorial", IEEE Circuits and Systems Magazine , 11(4), pp. 24-34, Nov. 2011

2010

  1. D. Oh and K.K. Parhi, "Minsum Decoder Architecture with Reduced Word-Length for LDPC Codes", IEEE Trans. Circuits and Systems-I: Regular Papers, 57(1), pp. 105-115, Jan. 2010

  2. D. Oh and K.K. Parhi, "Low-Complexity Switch Networks for Reconfigurable LDPC Decoders", IEEE Trans. VLSI Systems , 18(1), pp. 85-94, Jan. 2010

  3. Y. Liu, T. Zhang and K.K. Parhi, "Computation Error Analysis in Digital Signal Processing System with Overscaled Supply Voltage", IEEE Trans. VLSI Systems , 18(4), pp. 517-526, Apr. 2010

  4. A.E. Cohen and K.K. Parhi, "Fast Elliptic Curve Cryptography Acceleration for GF(2^m) on 32-Bit Processors", Springer Journal of Signal Processing Systems , 60(1), pp. 31-45, July 2010

2009

  1. E. Saberinia, J. Tang, A.H. Tewfik, and K.K. Parhi, "Pulsed OFDM Modulation for Ultra Wideband Communications", IEEE Trans. on Vehicular Technology , 58(2), pp. 720-726, Feb. 2009

  2. S. Park, K.K. Parhi, and S.-C. Park, "Probabilistic Spherical Detection and VLSI Implementation for Multiple Antenna Systems", IEEE Trans. Circuits and Systems-I: Regular Papers, 56(3), pp. 685-698, March 2009

  3. J. Chen, Y. Gu and K.K. Parhi, "Novel FEXT Cancellation and Equalization for High-Speed Ethernet Transceivers", IEEE Trans. Circuits and Systems-I: Regular Papers, 56(6), pp. 1272-1285, June 2009

  4. D. Oh and K.K. Parhi, "Low-Complexity Decoder Architecture for Low-density Parity Check Codes", Journal of VLSI Signal Processing Systems , 56, pp. 217-228, June 2009

  5. R. Liu and K.K. Parhi, "Low-Latency Low-Complexity Architectures for Viterbi Decoders", IEEE Trans. Circuits and Systems-I: Regular Papers, 56(10), pp. 2315-2324, Oct. 2009

  6. A.E. Cohen and K.K. Parhi, "A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802.3an (10GBase-T) Ethernet", IEEE Trans. Signal Processing, 57(10), pp. 4085-4094, Oct. 2009

  7. M. Garrido, K.K. Parhi, and J. Grajal, "A Pipelined FFT Architecture for Real-Valued Signals", IEEE Trans. Circuits and Systems-I: Regular Papers, 56(12), pp. 2634-2643, Dec. 2009

2008

  1. C. Cheng and K.K. Parhi, "High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform", IEEE Trans. on Signal Processing, 56(1), pp. 393-403, Jan. 2008

  2. Y. Gu and K.K. Parhi, "Design of Parallel Tomlinson-Harashima Precoders", IEEE Trans. Circuits and Systems-II: Express Briefs, 55(5), pp. 447-451, May 2008

  3. J. Chen, Y. Gu and K.K. Parhi, "Low Complexity ECHO And NEXT Cancellers for High-Speed Ethernet Transceivers", IEEE Trans. Circuits and Systems-I: Regular Papers, 55(9), pp. 2827-2840, Oct. 2008

  4. C. Cheng and K.K. parhi, "Hardware-Efficient Low-Latency Architecture for High-Throughput Rate Viterbi Decoders", IEEE Trans. Circuits and Systems-II: Express Briefs, 55(12), pp. 1254-1258, Dec. 2008

2007

  1. K.-J. Cho, J.-S. Park, B.-K. Kim, J.-G. Chung and K.K. Parhi, "Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter", IEEE Trans. on Circuits and Systems, Part-II: Express Briefs, 54(1), pp. 19-23, Jan. 2007

  2. Y. Gu and K.K. Parhi, "Pipelined Parallel Decision Feedback Decoders for High-Speed Ethernet over Copper", IEEE Trans. on Signal Processing, 55(2), pp. 707-715, Feb. 2007

  3. C. Cheng and K.K. Parhi, "Low Cost Parallel FIR Filter Structures with 2-Stage Parallelism", IEEE Trans. Circuits and Systems-I: Regular Papers, 54(2), pp. 280-290, Feb. 2007

  4. C. Cheng and K.K. Parhi, "Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform", IEEE Trans. Circuits and Systems-I: Regular Papers, 54(4), pp. 791-806, Apr. 2007

  5. Y. Gu and K.K. Parhi, "High-Speed Architecture Design of Tomlinson-Harashima Precoders", IEEE Trans. Circuits and Systems-I: Regular Papers, 54(9), pp. 1929-1937, Sep. 2007

  6. C. Cheng and K.K. Parhi, "High-Throughput VLSI Architecture for FFT Computation", IEEE Trans. Circuits and Systems-II: Express Briefs, 54(10), pp. 863-867, Oct. 2007

2006

  1. C. Cheng and K.K. Parhi, "Hardware Efficient Fast Computation of the Discrete Fourier Transform", Springer Journal of VLSI Signal Processing, pp. 159-171, 42(2), Feb. 2006

  2. Y. Gu and K.K. Parhi, "Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper", Journal of VLSI Signal Processing Systems, 44(3), pp. 211-221, March 2006

  3. L. Gao and K.K. Parhi, "Models for Architectural Power and Power Grid Noise Analysis on Data Bus", Journal of VLSI Signal Processing Systems, 44(2), pp. 25-46, August 2006

  4. J.-H. Lin and K.K. Parhi, "Parallelization of Context Based Adaptive Binary Arithmetic Coders", IEEE Trans. on Signal Processing, 54(10), pp. 3702-3711, Oct. 2006

  5. C. Cheng and K.K. Parhi, "High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining and Retiming", IEEE Trans. Circuits and Systems-II: Express Briefs, 53(10), pp. 1017-1021, Oct. 2006

  6. X. Zhang and K.K. Parhi, "On the Optimum Constructions of Composite Field for the AES Algorithm", IEEE Trans. Circuits and Systems-II: Express Briefs, 53(10), pp. 1153-1157, Oct. 2006

  7. C. Cheng and K.K. Parhi, "Hardware Efficient Fast DCT Based on Novel Cyclic Convolution Structures", IEEE Trans. on Signal Processing, 54(11), pp. 4419-4434, Nov. 2006

2005

  1. Y. Chen and K.K. Parhi, "On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes" Journal of VLSI Signal Processing Systems, 39(1-2), pp. 35-47, Jan. 2005

  2. X. Zhang and K.K. Parhi, "Fast Factorization Architecture in Soft-Decision Reed-Solomon Decoding", IEEE Trans. on VLSI Systems, 13(4), pp. 413-426, Apr. 2005

  3. K.K. Parhi, "Design of Multi-Gigabit Multiplexer Loop Based Decision Feedback Equalizers", IEEE Trans. on VLSI Systems, 13(4), pp. 489-493, Apr. 2005

  4. C. Cheng and K.K. Parhi, "A Novel Systolic Array Structure for DCT", IEEE Trans. on Circuits and Systems, Part-II: Express Briefs, 52(5), pp. 366-369, July 2005

  5. X. Zhang and K.K. Parhi, "High-Speed Architectures for Parallel Long BCH Encoders", IEEE Trans. on VLSI Systems, 13(7), pp. 872-877, July 2005

  6. K.K. Parhi, "Fron the Desk of the Editor-in-Chief," IEEE Trans. Circuits and Systems, Part-I: Regular Papers, 52(12), pp. 2509-2510, December 2005

2004

  1. K.K. Parhi, "The Editor's Corner," IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(1), pp. 1-2, Jan. 2004

  2. Z. Chi, L. Song and K.K. Parhi, "On the Performance/Complexity Tradeoff in Block Turbo Decoder Design," IEEE Communications Letters, Vol. 52, No. 2, pp. 173-175, Feb. 2004

  3. K.K. Parhi, "An Improved Pipelined MSB-First Add-Compare-Select Unit Structure for Viterbi Decoders", IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(3), pp. 504-511, March 2004

  4. K. K. Parhi, "Eliminating the Fanout Bottleneck in Parallel Long BCH Encoders", IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(3), pp. 512-516, March 2004

  5. T. Zhang and K.K. Parhi, "Joint (3,k)-regular LDPC Code and Decoder/Encoder Design", IEEE Trans. Signal Processing, 52(4), pp. 1065-1079, April 2004

  6. K.-J. Cho, K.-C. Lee, J.-G. Chung, and K.K. Parhi, "Design of Low-Error Fixed Width Modified Booth Multiplier", IEEE Trans. on VLSI Systems, 12(5), pp. 522-531, May 2004

  7. J. Kong and K.K. Parhi, "Low-Latency Architectures for High-Throughput Viterbi Decoders", IEEE Trans. on VLSI Systems, 12(6), pp. 642-651, June 2004

  8. Y. Chen and K.K. Parhi, "Small Area Parallel Chien search Architectures for Long BCH Codes", IEEE Trans. on VLSI Systems, 12(5), pp. 545-549, May 2004

  9. Y. Chen and K.K. Parhi, "Overlapped Message Passing of Quasi-Cyclic Low-Density Parity Check Codes", IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(6), pp. 1106-1113, June 2004

  10. J. Ma and K.K. Parhi, "Pipelined CORDIC Based State-Space Orthogonal Recursive Digital Filters using Matrix Look-Ahead", IEEE Trans. Signal Processing, 52(7), pp. 2102-2119, July 2004

  11. V. Sundararajan, S. Sapatnekar and K.K. Parhi, "A New Approach for Integration of Min-Area Retiming and Min-Delay Padding for Simultaneously Addressing Short Path and Long Path constraints", ACM Trans. on TODAES, 9(3), pp. 273-289, July 2004

  12. C. Cheng and K.K. Parhi, "Hardware Efficient Fast Parallel FIR Filter Structures Based on Iterated Short Convolution", IEEE Trans. on Circuits and Systems, Part-I: Regular Papers, 51(8), pp. 1492-1500, Aug. 2004

  13. X. Zhang and K.K. Parhi, "High-Speed VLSI Architectures for the AES Algorithm", IEEE Trans. on VLSI Systems, 12(9), pp. 957-967, Sep. 2004

  14. Z. Chi, Z. Wang and K.K. Parhi, "On the Better Protection of Short Frame Turbo Codes", IEEE Trans. on Communications, 52(9), pp. 1435-1439, Sept. 2004

2003

  1. T. Sansaloni, J. Valls and K.K. Parhi, "Digit-Serial Complex Number Multipliers on FPGAs", Journal of VLSI Signal Processing, Vol. 33(1-2), pp. 105-115, Jan. 2003

  2. Z. Wang and K.K. Parhi, "Performance Improvement and Implementation Issues of Turbo/SOVA Decoders", IEEE Trans. on Communications, Vol. 51(4), pp. 570-579, April 2003

  3. T. Zhang and K.K. Parhi, "An FPGA Implementation of (3,6) Regular Low-Density Parity-Check Code Decoder", Eurasip Journal on Applied Signal Processing, 2003(6), pp. 530-542, May 2003

  4. V. Sundararajan and K.K. Parhi, "Synthesis of Minimum Area Folded Architectures for Rectangular Multi-Dimensional Multirate DSP Systems", IEEE Trans. on Signal Processing, 51(7), pp. 1954-1965, July 2003

  5. Y.-N. Chang and K.K. Parhi, "An Efficient Pipelined FFT Implementation", IEEE Trans. on Circuits and Systems: Part-II: Analog and Digital Signal Processing, Vol. 50(6), pp. 322-325, June 2003

  6. B. Sahoo and K.K. Parhi, "A Low Power Correlator for CDMA Wireless Systems", Journal of VLSI Signal Processing, 35(1), pp. 105-112, August 2003

  7. L. Gao, K.K. Parhi and J. Ma, "Relaxed Annihilation-Reordering Look-Ahead QRD-RLS Adaptive Filters", Journal of VLSI Signal Processing, Vol. 35(2), pp. 119-135, Sept. 2003

  8. J. Kong and K.K. Parhi, "Interleaved Convolutional Code and its Viterbi Decoder Architecture", EURASIP Journal on Applied Signal Processing, Vol. 2003(13), pp. 1328-1334, 2003

  9. Y. Chen and K.K. Parhi, "Low Complexity Decoding Algorithms of Block Turbo Coded System" with Antenna Diversity, EURASIP Journal on Applied Signal Processing, Vol. 2003(13), pp. 1335-1345, 2003

  10. S.-M. Kim, J.-G. Chung and K. K. Parhi, "Low error CSD Fixed-Width Multiplier with Efficient Sign Extension", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 50(3), pp. 984-993, December 2003

2002

  1. W.L. Freking and K.K. Parhi, "Performance-Scalable Array Architectures for Modular Multiplication", Journal of VLSI Signal Processing Systems, 31(2), pp. 101-116, April 2002

  2. V. Sundararajan, S. Sapatnekar and K.K. Parhi, "Fast and Exact Transistor Sizing Based on Iterative Relaxation", IEEE Trans. on CAD, 21(5), pp. 568-581, May 2002

  3. M. Kuhlmann and K.K. Parhi, "P-CORDIC: A Precomputation Based CORDIC Algorithm for the Circular Mode", Eurasip Journal on Applied Signal Processing, 2002(9), pp. 936-943, Sept. 2002

  4. J.G. Chung and K.K. Parhi, "Frequency spectrum based low-area low-power parallel FIR filter design", Eurasip Journal on Applied Signal Processing, 2002(9), pp. 944-953, Sept. 2002

  5. J. Valls, M. Kuhlmann, K.K. Parhi, "Evaluation of CORDIC Algorithms for FPGA design", Journal of VLSI Signal Processing, 32(3), pp. 207-222, Nov. 2002

  6. Z. Wang, Z. Chi and K.K. Parhi, "Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders", IEEE Trans. on VLSI Systems, 10(12), pp. 902-912, Dec. 2002

  7. Z. Wang and K.K. Parhi, "On-Line Extraction of Soft Decoding Information and its Applications in VLSI Turbo Codes", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing ,49(12), pp. 760-769, Dec. 2002

  8. X. Zhang and K.K. Parhi, "Hardware Implementation of Advanced Encryption Standard Algorithm", IEEE CAS Magazine, 2(4), pp. 24-46, Dec. 2002

  9. I. Ben Dhaou, K.K. Parhi and H. Tenhunen, "Energy Efficient Signaling in Deep-submicron Technology", VLSI Design: Special Issue on Timing Analysis and Optimization for Deep Sub-Micron ICs, Vol. 15(3), pp. 563-586, 2002

2001

  1. J. Ma, K.K. Parhi and E.F. Deprettere, "A Unified Algebraic Transformation Approach for Parallel Recursive and Adaptive Filtering and SVD Algorithms", IEEE Trans. on Signal Processing, 49(2), pp. 424-437, Feb. 2001

  2. M. Kuhlmann and K.K. Parhi, "A Novel Low-Power Shared Division and Square-Root using the GST Algorithm", VLSI Design, 12(3), pp. 365-376, 2001

  3. M.E. Zervakis, V. Sundararajan and K.K. Parhi, "Vector Processing of Wavelet Coefficients for Robust Image Denoising", Journal of Image and Vision Computing, Elsevier, 19(7), pp. 435-450, May 2001

  4. T. Zhang and K.K. Parhi, "A Novel Systematic Design Approach for Mastrovito Multipliers over GF(2^m)", IEEE Trans. on Computers, 50(7), pp. 734-749, July 2001

  5. Z. Chi, J. Ma and K.K. Parhi, "Hybrid Annihilation Transformation (HAT) for Pipelining QRD Based Least Square Adaptive Filters", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 48(7), pp. 661-674, July 2001

  6. K.K. Parhi, "Low-Power Implementation of DSP Systems", IEEE Trans. on Circuits and Systems, Part-I: Fundamental Theory and Applications, 48(10), pp. 1214-1224, October 2001

  7. Z. Wang, H. Suzuki and K.K. Parhi, "Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders", Journal of VLSI Signal Processing, 29(3), pp. 209-222, November 2001

2000

  1. J.H. Satyanarayana and K.K. Parhi, "Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation", IEEE Trans. on VLSI Systems, 8(2), pp. 148-159, Apr. 2000

  2. L. Song, K.K. Parhi, I. Kuroda, T. Nishitani, "Hardware/Software Codesign of Finite Field Datapath for Low-Energy Reed-Solomon Codecs", IEEE Trans. on VLSI Systems, 8(2), pp. 160-172, Apr. 2000

  3. J. Satyanarayana and K.K. Parhi, "Power Estimation of Digital Datapaths using HEAT Tool", IEEE Design and Test Magazine, 17(2), pp. 101-110, April-June 2000

  4. Y.-N. Chang, H. Suzuki and K.K. Parhi, "A 2 Mb/s 256-State 10 mW Rate-1/3 Viterbi Decoder," IEEE Journal of Solid State Circuits, Vol. 35, No. 6, pp. 826-834, June 2000

  5. J.G. Chung, H. Kim and K.K. Parhi, "Angle-Constrained IIR Filter Pipelining for Reduced Roundoff Errors", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 47(6), pp. 555-559, June 2000

  6. Y.-N. Chang and K.K. Parhi, "High-Performance Digit-Serial Complex Multiplier", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 47(6), pp. 570-572, June 2000

  7. A. Shalash and K.K. Parhi, "Power-Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications", Journal of VLSI Signal Processing, 25(3), pp. 199-213, July 2000

  8. J. Ma, K.K. Parhi and E.F. Deprettere, "Annihilation-Reordering Look-Ahead Pipelined CORDIC Based RLS Adaptive Filters and Their Application to Adaptive Beamforming", IEEE Trans. on Signal Processing, 48(8), pp. 2414-2431, Aug. 2000

  9. J. Ma, K.K. Parhi, G.J. Hekstra and E.F. Deprettere, "Efficient Implementations of Pipelined CORDIC Based IIR Digital Filters using Fast Orthonormal Micro-rotations", IEEE Trans. on Signal Processing, 48(9), pp. 2712-2716, Sep. 2000

  10. J. Ma, K.K. Parhi and E.F. Deprettere, "Pipelined CORDIC Based Cascade Orthogonal IIR Digital Filters", IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 47(11), pp. 1238-1253, Nov. 2000

  11. L. Gao and K.K. Parhi, "Hierarchical Pipelining and Folding of QRD-RLS Adaptive Filters and Its Application to Digital Beamforming," IEEE Trans. on Circuits and Systems, Part-II: Analog and Digital Signal Processing, 47(12), pp. 1503-1519, Dec. 2000

1999

  1. H.R. Srinivas and K.K. Parhi, "A Radix 2 Shared Division/Square-Root Algorithm and its VLSI Architecture," Journal of VLSI Signal Processing, 21(1), pp. 37-60, May 1999

  2. T.C. Denk and K.K. Parhi, "Two-Dimensional Retiming [VLSI Design]," IEEE Trans. on VLSI Systems, 7(2), pp. 198-211, June 1999

  3. A.F. Shalash and K.K. Parhi, "Multi-Dimensional Carrierless AM/PM Systems for Digital Subscriber Loops," IEEE Trans. on Communications, 47(11), pp. 1655-1667, Nov. 1999

  4. K.K. Parhi, "Low-Energy CSMT Carry-Generators and Binary Adders," IEEE Trans. on VLSI Systems, 7(4), pp. 450-462, Dec. 1999

1998

  1. S. Jain, L. Song and K.K. Parhi, "Efficient Semi-Systolic VLSI Architectures for Finite Field Arithmetic," IEEE Trans. on VLSI Systems, 6(1), pp. 101-113, March 1998

  2. M. Majumdar and K.K. Parhi, "Design of Data Format Converters using Two-Dimensional Register Allocation," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 45(4), pp. 504-508, April 1998

  3. L. Song and K.K. Parhi, "Low-Energy Digit-Serial/Parallel Finite Field Multipliers", Journal of VLSI Signal Processing, 19(2), pp. 149-166, June 1998

  4. T.C. Denk and K.K. Parhi, "Exhaustive Scheduling and Retiming of Digital Signal Processing Systems," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 45(7), pp. 821-838, July 1998

  5. L. Montalvo, K.K. Parhi, and A. Guyot, "New Svoboda-Tung Division," IEEE Trans. on Computers, 47(9), pp. 1014-1020, Sept. 1998

  6. Y.-N. Chang, C.Y. Wang, and K.K. Parhi, "Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units," Journal of VLSI Signal Processing, 19(3), pp. 243-256, Aug. 1998

  7. K. Ito, L.E. Lucke and K.K. Parhi, "ILP Based Cost-Optimal DSP Synthesis with Module Selection and Data Format Conversion," IEEE Trans. on VLSI Systems, 6(4), pp. 582-594, Dec. 1998

  8. T.C. Denk and K.K. Parhi, "Synthesis of Folded Pipelined Architectures for Multirate DSP Algorithms," IEEE Trans. on VLSI Systems, 6(4), pp. 595-607, Dec. 1998

  9. Y.-N. Chang, J.H. Satyanarayana and K.K. Parhi, "Systematic Design of High-Speed and Low-Power Digit-Serial Multipliers," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 45(12), pp. 1585-1596, Dec. 1998

1997

  1. H.R. Srinivas, K.K. Parhi, and L. Montalvo, "Radix-2 Division with Over-Redundant Quotient Selection," IEEE Trans. on Computers, 46(1), pp. 85-92, Jan. 1997

  2. T.C. Denk and K.K. Parhi, "VLSI Architectures for Lattice Structure Based Orthonormal Discrete Wavelet Transforms," IEEE Transactions on Circuits and Systems, Part - II: Analog and Digital Signal Processing, 44(2), pp. 129-132, Feb. 1997

  3. B. Fu and K.K. Parhi, "Generalized Multiplication Free Arithmetic Codes," IEEE Transactions on Communications, 45(5), pp. 497-501, May 1997

  4. K.J. Raghunath and K.K. Parhi, "Finite Precision Error Analysis of QRD-RLS and STAR-RLS Adaptive Filters," IEEE Transactions on Signal Processing}, 45(5), pp. 1193-1209, May 1997

  5. K. Ito and K.K. Parhi, "A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis," Journal of VLSI Signal Processing, 16(1), pp.  57-72, May 1997

  6. J.H. Satyanarayana and K.K. Parhi, "A Theoretical Approach to Estimation of Bounds on Power Consumption in Digital Multipliers," IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing, 44(6), pp. 473-481, June 1997

  7. D.A. Parker and K.K. Parhi, "Low Area/Power Parallel FIR Digital Filter Implementations," Journal of VLSI Signal Processing, 17(1), pp. 75-92, Sept. 1997

  8. Y. Li and K.K. Parhi, "STAR Recursive Least Square Lattice Adaptive Filters," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 44(12), pp. 1040-1054, December 1997

1996

  1. T.C. Denk and K.K. Parhi, "Lower Bounds on Memory Requirements for Statically Scheduled DSP Programs," Journal of VLSI Signal Processing, 12(3), pp. 247-264. June 1996

  2. K.J. Raghunath, and K.K. Parhi, "Pipelined RLS Adaptive Filtering using Scaled Tangent Rotations (STAR)," IEEE Transactions on Signal Processing, 44(10), pp. 2591-2604, October 1996

1995

  1. K.K. Parhi, "High-Level Algorithm and Architecture Transformations for DSP Synthesis,"   Journal of VLSI Signal Processing, 9(1), pp. 121-143, January 1995

  2. C.-Y. Wang, and K.K. Parhi, "High-Level DSP Synthesis using Concurrent Transformations, Scheduling, and Allocation," IEEE Transactions on Computer Aided Design, 14(3), pp. 274-295, March 1995

  3. J.-G. Chung, and K.K. Parhi, "Scaled Normalized Lattice Digital Filters," IEEE Transactions on Circuits and Systems - Part II: Analog and Digital Signal Processing, 42(4), pp. 278-282, April 1995

  4. N.R. Shanbhag, and K.K. Parhi, "Pipelined Adaptive DFE Architectures using Relaxed Look-Ahead," IEEE Trans. on Signal Processing, 43(6), pp. 1368-1385, June 1995

  5. H.R. Srinivas, and K.K. Parhi, "A Fast Radix-4 Division Algorithm," IEEE Transactions on Computers, 44(6), pp. 826-831, June 1995

  6. J.-G. Chung, H. Kim and K.K. Parhi, "Pipelined Lattice WDF Design for Wideband Filters," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, 42(9), pp. 616-618, September 1995

  7. C.-Y. Wang, and K.K. Parhi, "Resource Constrained Loop List Scheduler for DSP Algorithms," Journal of VLSI Signal Processing, 11(1/2), pp. 75-96, October 1995

  8. K. Ito and K.K. Parhi, "Determining the Minimum Iteration Period of an Algorithm," Journal of VLSI Signal Processing, 11(3), pp. 229-244, December 1995

1994

  1. K.K. Parhi, F.H. Wu, and K. Ganesan, "Sequential and Parallel Neural Network Vector Quantizers," IEEE Transactions on Computers, 43(1), pp. 104-109, January 1994

  2. J.-G. Chung, and K.K. Parhi, "Pipelining of Lattice IIR Digital Filters," IEEE Transactions on Signal Processing, 42(4), pp. 751-761, April 1994

  3. L.E. Lucke, and K.K. Parhi, "Parallel Processing Architectures for Rank-Order and Stack Filters," IEEE Transactions on Signal Processing, 42(5), pp. 1178-1189, May 1994

  4. N.R. Shanbhag, and K.K. Parhi, "Finite Precision Analysis of the ADPCM Coder," IEEE Transactions on Circuits and Systems-Part II: Analog and Digital Signal Processing, 41(5), pp. 364-368, May 1994

  5. K.K. Parhi, "Calculation of Minimum Number of Registers in Arbitrary Life Time Chart," IEEE Circuits and Systems Transactions - Part II: Analog and Digital Signal Processing, 41(6), pp. 434-436, June 1994

  6. N.R. Shanbhag, and K.K. Parhi, "Corrections to "Finite Precision Analysis of the ADPCM Coder,"   IEEE Transactions on Circuits and Systems-Part II: Analog and Digital Signal Processing,  41(7), pp. 493, July 1994

  7. G.B. Adams III, E.J. Coyle, L. Lin, L.E. Lucke, and K.K. Parhi, "Input Compression and Efficient VLSI Architectures for Rank-Order and Stack Filters," Signal Processing,  38, pp. 441-453, August 1994

  8. H.R. Srinivas, B. Vinnakota, and K.K. Parhi, "A C-Testable Carry-Free Divider," IEEE Trans. on VLSI Systems, 2(4), pp. 472-488, December 1994

1993

  1. N.R. Shanbhag, and K.K. Parhi, "A Pipelined Adaptive Differential Vector Quantizer for Low-Power Speech Coding Applications," IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing, 40(5), May 1993, pp. 347-349

  2. N.R. Shanbhag, and K.K. Parhi, "A Pipelined Adaptive Lattice Filter Architecture," IEEE Trans. on Signal Processing, 41(5), May 1993, pp. 1925-1939

  3. K.J. Raghunath, and K.K. Parhi, "Parallel Adaptive Decision Feedback Equalizers," IEEE Transactions on Signal Processing, 41(5), May 1993, pp. 1956-1961

  4. K.K. Parhi, and T. Nishitani, "VLSI Architectures for Discrete Wavelet Transforms," IEEE Trans. on VLSI Systems, 1(2), June 1993, pp. 191-202

  5.  L.E. Lucke, and K.K. Parhi, "Data-Flow Transformations for Critical Path Time Reduction For High-Level DSP Synthesis," IEEE Transactions on Computer Aided Design  of Integrated Circuits And Systems, 12(7), July 1993,  pp. 1063-1068

  6. N.R. Shanbhag, and K.K. Parhi, "Relaxed Look-Ahead Pipelined LMS Adaptive Filters and Their Application to ADPCM Coder," IEEE Transactions on Circuits and Systems, Part II: Analog and Digital Signal Processing, Vol. 40(12), December 1993, pp. 753-766

1992

  1. K.K. Parhi, C.Y. Wang, A.P. Brown, "Synthesis of Control Circuits in Folded Pipelined DSP Architectures," IEEE Journal of Solid State Circuits, Vol. 27, No. 1, January 1992, pp. 29-43

  2. M. Hatamian and K.K. Parhi, "An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip," IEEE Journal of Solid State Circuits, Vol. 27, No. 2, February 1992, pp. 175-183

  3. H.R. Srinivas, and K.K. Parhi, "High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation," Journal of  VLSI Signal Processing,  Vol. 4, No. 2/3, 1992, pp. 177-198

  4. H.R. Srinivas, and K.K. Parhi, "A Fast VLSI Adder Architecture," IEEE Journal of Solid State Circuits, Vol. 27, No. 5, May 1992, pp. 761-767

  5. K.K. Parhi, "High-Speed VLSI Architectures for Huffman and Viterbi Decoders," IEEE Trans. on Circuits and Systems, Part II: Analog and Digital Signal Processing, Vol. 39, No. 6, June 1992, pp. 385-391

  6. K.K. Parhi, "Video Data Format Converters Using Minimum Number of Registers," IEEE Transactions on Circuits and Systems For Video Technology, Vol. 2, No. 2, June 1992, pp. 255-267

  7. K.K. Parhi, "Systematic Synthesis of DSP Data Format Converters using Life-Time Analysis and Forward-Backward Register Allocation,"   IEEE  Trans. on Circuits and Systems, Part II: Analog  and Digital Signal Processing, Vol. 39, No. 7, July 1992, pp. 423-440

1991

  1. K.K. Parhi, and D.G. Messerschmitt, "Static Rate-Optimal Scheduling of Iterative Data Flow Programs via Optimum Unfolding," IEEE Trans. on Computers, Vol. 40(2), February 1991, pp. 178-195

  2. K.K. Parhi, "A Systematic Approach for Design of Digit-Serial Signal Processing Architectures," IEEE Trans. on Circuits and Systems, Vol. 38, No. 4, April 1991, pp. 358-375

  3. K.K. Parhi, "Pipelining In Dynamic Programming Architectures," IEEE Trans. on Signal Processing, Vol. 39, No. 6, June 1991, pp. 1442-1450

  4. K.K. Parhi, "Finite Word Effects in Pipelined Recursive Filters," IEEE Trans. on Signal Processing, Vol. 39, No. 6, June 1991, pp. 1450-1454

  5. K.K. Parhi, "Pipelining in Algorithms with Quantizer Loops," IEEE Trans. on Circuits and Systems, Vol. 38, No. 7, July 1991, pp. 745-754

  6. K.K. Parhi, "Technology for the 90s: VLSI Signal and Image Processing Systems," IEEE Circuits and Devices Magazine (special technology forecast  issue), 7(4), July 1991 (invited article), pp. 16-17

  7. K.K. Parhi, "Research on VLSI For Digital Video Systems in Japan", Asian Scientific Information Bulletin of the Office of Naval Research Office, 16(4), October - December 1991, pp. 93-98

1989

  1. K.K. Parhi, and D.G. Messerschmitt, "Concurrent Architectures for Two-Dimensional Recursive Digital Filtering," IEEE Trans. on Circuits and Systems, Vol. CAS-36(6), June 1989, pp. 813-829

  2. K.K. Parhi, and D.G. Messerschmitt, "Pipeline Interleaving and Parallelism in recursive Digital Filters, Part I: Pipelining using Scattered Look-Ahead and Decomposition," IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 37(7), July 1989, pp. 1099-1117

  3. K.K. Parhi, and D.G. Messerschmitt, "Pipeline Interleaving and Parallelism in recursive Digital Filters, Part II: Pipelined Incremental Block Filtering,"  IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 37(7), July 1989, pp. 1118-1135

  4.  K.K. Parhi, "Algorithm Transformation Techniques for Concurrent Processors," Proceedings of the IEEE, Special Issue on Supercomputer Technology, Vol. 77(12), December 1989, pp. 1879-1895

1987

  1. K.K. Parhi and D.G. Messerschmitt, "Concurrent Cellular VLSI Adaptive Filter Architectures," IEEE Transactionson Circuits and Systems, Vol. CAS-34, No. 10, October 1987, pp. 1141-1151

  2. K.K. Parhi and R.S. Berkowitz, "On Optimizing Importance SamplingSimulations," IEEE Transactions of Circuits and Systems, Vol. CAS-34, No. 12, December 1987, pp. 1558-1563