Title: High Performance, Low Complexity VLSI Design of Turbo Decoders

Abstract:

Turbo codes invented in 1993 have become one of the important research topics in communication and coding societies since their performance is close to the theoretical limit. In terms of applications, Turbo codes have been decided to be used in 3rd generation W-CDMA systems in many countries. In such cost sensitive applications, design of low cost VLSI Turbo decoders is of great interest.

This thesis considers various VLSI implementation issues of Turbo decoders and develops efficient approaches for improving decoder performance, interleaver design, adaptive decoding and high speed decoding of Turbo codes.

For maximum a posterior probability (MAP)-based Turbo decoders, an efficient state metrics normalization scheme is proposed. The best quantization schemes are presented for various variables considering trade-offs between decoder performance and hardware complexity. We also develop a novel adaptive decoding approach, which achieves very high power-down efficiency with negligible hardware overhead. There is no performance degradation and no introduced latency. A low power Turbo decoder chip based on the serial decoding architecture is de- signed, which is probably the first Turbo decoder chip embedded with an efficient adaptive decoding function.

For soft output Viterbi algorithm (SOVA)-based Turbo decoders, two VLSI applicable approaches are proposed to improve the performance of Turbo decoders. It is shown that an extra coding gain of 0.5 dB can be obtained with the proposed performance improving approaches. Specifically, we show that, with finite wordlength implementation, new SOVA-based Turbo decoders can achieve almost the same coding gain as MAP-based Turbo decoders in some applications.

We develop an area-efficient two-level hierarchal interleaver archi- tecture, which performs at least as well as random-like interleavers while significantly reducing area requirement in VLSI implementation.

We also propose a new terminology, namely Turbo Decoding Metrics (TDMs). This is probably the first time to make it possible to provide soft information about decoded results instead of hard decision with CRC. Various application of TDMs are presented.

We develop a class of area-efficient high speed Turbo decoding schemes. A modified version of the partial storage of state metrics approach is presented and it is shown that the new approach would achieve a better trade-off in most practical applications. Two types of pipelined parallel decoding schemes are developed. The usefulness of hybrid parallel decoding schemes is pointed out. The application of pipeline interleaving to parallel Turbo decoding architectures is presented.

Chapters:  ......

For more information, contact Dr. Wang at edzfwang@yahoo.com