John Sartori

Assistant Professor

Research Area: Computer Engineering, VLSI, and Circuits

4-163 Keller Hall
612-625-0811
jsartori@umn.edu
http://www.ece.umn.edu/users/jsartori/

Area of Expertise:

Computer Architecture, Computer-Aided Design, Stochastic Computing, Low-Power Design and Architecture, Application-aware Design

Education:

Ph.D. Electrical and Computer Engineering (2012) University of Illinois at Urbana-Champaign
M.S. Electrical and Computer Engineering (2010) University of Illinois at Urbana-Champaign
B.S. Electrical Engineering (2006) University of North Dakota, Grand Forks

Honors/Awards:

NSF CAREER Award (2017)
Russell J. Penrose Excellence in Teaching Award (2017)
Best Paper Award (CAL 2013)
Intel Computer Engineering Fellowship
Best Paper Award Nomination (HPCA 2012)
Best Paper Award (CASES 2011)

Synopsis:

The underlying theme of my research has been to lay out a path into the future that allows us to continue to reap the benefits of Moore’s law. Toward this goal, my approach has been twofold. First, identify and address the primary bottlenecks that prevent the continuation of benefits from Moore’s law. Second, identify and address the disconnects between current hardware design and architecture methodologies and the computational usage models of the future.

Publications:

Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori. “Determining Application-specific Peak Power and Energy Requirements for Ultra-low-power Processors.” 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi’an, China, April 2017.

Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, and John Sartori. “Enabling Effective Module-oblivious Power Gating for Embedded Processors.” 23rd IEEE International Symposium on High-Performance Computer Architecture (HPCA), Austin, TX, February 2017.

Amrut Kapare, Hari Cherupalli, and John Sartori. “Automated Error Prediction for Approximate Sequential Circuits.” International Conference on Computer-Aided Design (ICCAD), Austin, TX, November 2016

Amoghavarsha Suresh and John Sartori. “Automated Algorithmic Error Resilience Based on Outlier Detection.” [Featured Article] IEEE Micro, Special Series on Harsh Chips, 2016

Hari Cherupalli, Rakesh Kumar, and John Sartori. “Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems.” 43rd ACM/IEEE International Symposium on Computer Architecture (ISCA), Seoul, Korea, June 2016.

John Sartori and Rakesh Kumar. “Branch and Data Herding: Reducing Control and Memory Divergence for Error-tolerant GPU Applications” IEEE Transactions on Multimedia (TMM) Special Issue on New Software / Hardware Paradigms for Error-tolerant Multimedia Systems, 2012.

John Sartori and Rakesh Kumar. “Exploiting Timing Error Resilience in Processor Architecture”. ACM Transactions on Embedded Computing Systems (TECS) Special Issue on Probabilistic Embedded Computing, 2012.

Andrew Kahng, Seokhyeong Kang, Rakesh Kumar, and John Sartori. “Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors”. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2012.

John Sartori and Rakesh Kumar. “Compiling for Energy Efficiency on Timing Speculative Processors”. 49th ACM/IEEE Design Automation Conference (DAC), 2012.

Joseph Sloan, John Sartori, and Rakesh Kumar. “Exploiting Application-Level Error Tolerance in Software Design for Stochastic Processors”. [Invited] 49th ACM/IEEE Design Automation Conference (DAC), 2012.

John Sartori, Ben Ahrens, and Rakesh Kumar. “Power Balanced Pipelines”. [Best Paper Award Nomination] 18th IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2012.

John Sartori and Rakesh Kumar. “Architecting Processors to Allow Voltage/Reliability Tradeoffs”. [Best Paper Award] International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), 2011.

Google Scholar Profile

PATENTS:
Rakesh Kumar, John Sartori, and Benjamin Ahrens. “Power Balanced Pipelines”. U.S. Provisional Patent 61/552,703, filed October 28, 2011.